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SLLS318C − NOVEMBER 1998 − REVISED JULY 2006
DGG PACKAGE
(TOP VIEW)
D
D
3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D17
D18
V
CC
1
48
47
46
45
44
43
42
41
40
39
38
D16
D15
D14
GND
D13
2
GND
D19
3
D
Three Data Channels and Clock
Low-Voltage Differential Channels In and
21 Data and Clock Low-Voltage TTL
Channels Out
4
D20
5
NC
6
LVDSGND
A0M
V
7
CC
D
D
D
Operates From a Single 3.3-V Supply
Tolerates 4-kV HBM ESD
D12
D11
D10
GND
8
A0P
9
A1M
10
11
12
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
A1P
LVDSV
37 D9
36
35 D8
CC
LVDSGND 13
A2M 14
V
CC
D
D
Consumes Less Than 1 mW When Disabled
Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
15
16
17
18
19
20
21
22
23
24
34
33
32
31
30
29
28
27
26
25
A2P
CLKINM
D7
D6
D
No External Components Required for PLL
CLKINP
GND
D5
LVDSGND
PLLGND
D
Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644
Standard
D4
PLLV
D3
CC
PLLGND
SHTDN
CLKOUT
D0
V
D
Improved Replacement for the DS90C364
and SN75LVDS86
CC
D2
D1
D
Improved Jitter Tolerance
GND
D
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
NC − Not connected
description
The SN65LVDS86AQ/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers
and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions
allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over
four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data
at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The
’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The
data bus appears the same at the input to the transmitter and output of the receiver with the data transmission
transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)
active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level
on this signal clears all internal registers to a low level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
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Copyright 2006, Texas Instruments Incorporated
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ꢏ ꢢ ꢟ ꢏꢐ ꢑꢫ ꢜꢛ ꢎ ꢍꢍ ꢣꢎ ꢝ ꢎ ꢞ ꢢ ꢏ ꢢ ꢝ ꢟ ꢦ
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