SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
FlatLink™ RECEIVER
Check for Samples: SN65LVDS86A-Q1
1
FEATURES
DGG PACKAGE
(TOP VIEW)
2
•
3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
D17
D18
GND
VCC
D16
D15
D14
GND
D13
VCC
D12
D11
D10
GND
D9
•
Suited for SVGA, XGA, or SXGA Display Data
Transmission From Controller to Display With
Very Low EMI
1
48
47
46
45
44
43
42
41
40
39
38
37
2
3
D19
D20
4
•
Three Data Channels and Clock Low-Voltage
Differential Channels In and 21 Data and Clock
Low-Voltage TTL Channels Out
5
NC
6
LVDSGND
A0M
7
•
•
•
Operates From a Single 3.3-V Supply
8
Tolerates 4-kV Human-Body Model (HBM) ESD
A0P
A1M
9
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
10
11
12
A1P
LVDSVCC
•
•
Consumes Less Than 1 mW When Disabled
Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
LVDSGND 13
36 VCC
14
15
16
17
18
19
20
21
22
23
24
35
34
33
32
31
30
29
28
27
26
25
A2M
A2P
D8
D7
•
•
No External Components Required for PLL
CLKINM
CLKINP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
D6
GND
D5
Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644 Standard
•
Improved Replacement for the SN75LVDS86
and NSC DS90C364
D4
D3
VCC
D2
•
•
Improved Jitter Tolerance
Qualified for Automotive Applications
D1
GND
NC − Not connected
DESCRIPTION
The SN65LVDS86A FlatLink™ receiver contains three serial-in 7-bit parallel-out shift registers and four
low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt
of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four
balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a
lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The
SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low
level on this signal clears all internal registers to a low level.
The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
5秒后页面跳转
英伟达新AI芯片Rubin或提前半年亮相
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
三星深化印度制造布局，供应链本地化进程加速
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
