SN75LVDS84A, SN65LVDS84AQ
FLATLINK TRANSMITTER
SLLS354E – MAY 1999 – REVISED JANUARY 2001
DGG PACKAGE
(TOP VIEW)
21:3 Data Channel Compression at up to
196 Million Bytes per Second Throughput
Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With Very Low EMI
D4
D3
1
48
47
46
45
44
43
42
41
40
39
38
V
D2
2
CC
D5
GND
D1
3
21 Data Channels Plus Clock In
D6
4
Low-Voltage TTL Inputs and 3 Data
Channels Plus Clock Out Low-Voltage
Differential Signaling (LVDS) Outputs
GND
D7
D0
5
NC
6
D8
LVDSGND
Y0M
Y0P
Y1M
Y1P
7
Operates From a Single 3.3-V Supply and
89 mW (Typ)
V
8
CC
D9
D10
9
10
11
Ultralow-Power 3.3-V CMOS Version of the
SN75LVDS84. Power Consumption About
One Third of the ’LVDS84
GND
D11 12
D12 13
NC 14
37 LVDSV
CC
36 LVDSGND
35 Y2M
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20 Mil Terminal
Pitch
15
16
17
18
19
20
21
22
23
24
34
33
32
31
30
29
28
27
26
25
D13
D14
GND
D15
D16
D17
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
Consumes Less Than 0.54 mW When
Disabled
Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
PLLV
CC
No External Components Required for PLL
V
PLLGND
SHTDN
CLKIN
D20
CC
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D18
D19
GND
SSC Tracking Capability of 3% Center
Spread at 50-kHz Modulation Frequency
NC – Not Connected
Improved Replacement for SN75LVDS84
and NSC’s DS90CF363A 3-V Device
Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
description
The SN75LVDS84AandSN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift
registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.
The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The
threeserialstreamsandaphase-lockedclock(CLKOUT)arethenoutputtoLVDSoutputdrivers. Thefrequency
of CLKOUT is the same as the input clock, CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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