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SN65LVDS84AQ-Q1 PDF预览

SN65LVDS84AQ-Q1

更新时间: 2024-11-25 12:15:03
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德州仪器 - TI /
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15页 223K
描述
FlatLink™ TRANSMITTER

SN65LVDS84AQ-Q1 数据手册

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SN65LVDS84AQ-Q1  
www.ti.com........................................................................................................................................................ SLLS766AAUGUST 2006REVISED APRIL 2008  
FlatLink™ TRANSMITTER  
1
FEATURES  
DGG PACKAGE  
(TOP VIEW)  
2
21:3 Data Channel Compression at up to  
196 Mbytes/s Throughput  
D4  
D3  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
Suited for SVGA, XGA, or SXGA Data  
Transmission From Controller to Display With  
Very Low EMI  
V
CC  
D2  
GND  
D1  
2
D5  
3
D6  
GND  
D7  
4
21 Data Channels Plus Clock In Low-Voltage  
TTL Inputs and 3 Data Channels Plus Clock  
Out Low-Voltage Differential Signaling (LVDS)  
Outputs  
D0  
5
NC  
6
D8  
LVDSGND  
Y0M  
Y0P  
Y1M  
Y1P  
7
V
CC  
8
Operates From a Single 3.3-V Supply and  
89 mW (Typ)  
D9  
D10  
GND  
D11  
9
10  
11  
12  
Packaged in Thin Shrink Small-Outline  
Package (TSSOP) With 20-Mil Terminal Pitch  
LVDSV  
CC  
Consumes Less Than 0.54 mW When Disabled  
D12 13  
36 LVDSGND  
Wide Phase-Lock Input Frequency Range:  
31 MHz to 75 MHz  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
D13  
D14  
GND  
D15  
D16  
D17  
Y2M  
Y2P  
No External Components Required for PLL  
CLKOUTM  
CLKOUTP  
LVDSGND  
PLLGND  
Outputs Meet or Exceed the Requirements of  
ANSI EIA/TIA-644 Standard  
SSC Tracking Capability of 3% Center Spread  
at 50-kHz Modulation Frequency  
PLLV  
CC  
V
CC  
PLLGND  
SHTDN  
CLKIN  
D20  
Improved Replacement for SN75LVDS84 and  
NSC DS90CF363A 3-V Device  
D18  
D19  
GND  
Qualified for Automotive Applications  
NC − Not Connected  
DESCRIPTION/ORDERING INFORMATION  
The SN65LVDS84AQ FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four  
low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of  
single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a  
compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.  
When transmitting, data bits D0–D20 are each loaded into registers of the SN65LVDS84AQ upon the falling  
edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices.  
The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The  
frequency of CLKOUT is the same as the input clock, CLKIN.  
The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same  
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The  
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and  
shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal  
registers to a low level.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
FlatLink is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006–2008, Texas Instruments Incorporated  

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