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SN65LVDS3486BD PDF预览

SN65LVDS3486BD

更新时间： 2024-11-17 23:03:07
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
20页 293K
描述
HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDS3486BD 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.82差分输出：NO
高电平输入电流最大值：0.00001 A输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm湿度敏感等级：1
功能数量：4端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：TOTEM-POLE最大输出低电流：0.004 A
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：6 ns
接收器位数：4座面最大高度：1.75 mm
子类别：Line Driver or Receivers最大压摆率：23 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mm

SN65LVDS3486BD 数据手册

 浏览型号SN65LVDS3486BD的Datasheet PDF文件第2页浏览型号SN65LVDS3486BD的Datasheet PDF文件第3页浏览型号SN65LVDS3486BD的Datasheet PDF文件第4页浏览型号SN65LVDS3486BD的Datasheet PDF文件第5页浏览型号SN65LVDS3486BD的Datasheet PDF文件第6页浏览型号SN65LVDS3486BD的Datasheet PDF文件第7页 
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B  
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B  
HIGH-SPEED DIFFERENTIAL RECEIVERS  
SLLS440A – OCTOBER 2000 – REVISED MAY 2001  
SN65LVDS32B  
SN65LVDT32B  
Meets or Exceeds the Requirements of  
ANSI EIA/TIA-644 Standard for Signaling  
Rates up to 400 Mbps  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
†
Operates With a Single 3.3-V Supply  
G
G
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
–2-V to 4.4-V Common-Mode Input Voltage  
Range  
4B  
4A  
4Y  
G
SN65LVDT32B  
ONLY (4 Places)  
1A  
1Y  
Differential Input Thresholds <50 mV With  
50 mV of Hysteresis Over Entire  
Common-Mode Input Voltage Range  
1Y  
G
1B  
2Y  
2A  
11 3Y  
10 3A  
2A  
2B  
Integrated 110-Ω Line Termination  
Resistors Offered With the LVDT Series  
2B  
2Y  
3Y  
4Y  
9
GND  
3B  
Propagation Delay Times 4 ns (typ)  
3A  
3B  
4A  
4B  
Active Fail Safe Assures a High-Level  
Output With No Input  
Bus-Pin ESD Protection Exceeds  
15 kV HBM  
Inputs Remain High-Impedance on Power  
Down  
SN65LVDS3486B  
SN65LVDT3486B  
Recommended Maximum Parallel Rate of  
200 M-Transfers/s  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
Available in Small-Outline Package With  
1,27 mm Terminal Pitch  
SN65LVDT3486B  
1B  
1A  
V
CC  
4B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
ONLY (4 Places)  
1A  
1B  
Pin-Compatible With the AM26LS32,  
MC3486, or µA9637  
1Y  
1Y  
4A  
1,2EN  
1,2EN  
2Y  
4Y  
description  
2A  
2B  
3,4EN  
2Y  
3Y  
4Y  
2A  
11 3Y  
10 3A  
This family of differential line receivers offers  
improved performance and features that imple-  
ment the electrical characteristics of low-voltage  
differential signaling (LVDS). LVDS is defined in  
the TIA/EIA-644 standard. This improved perfor-  
mance represents the second generation of  
receiver products for this standard, providing a  
better overall solution for the cabled environment.  
This generation of products is an extension to TI’s  
overall product portfolio and is not necessarily a  
replacement for older LVDS receivers.  
2B  
3A  
3B  
GND  
9
3B  
3,4EN  
4A  
4B  
SN65LVDS9637B  
SN65LVDT9637B  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
Improved features include an input common-  
mode voltage range 2 V wider than the minimum  
required by the standard. This will allow longer  
cable lengths by tripling the allowable ground  
noise tolerance to 3 V between a driver and  
receiver. TI has additionally introduced an even  
wider input common-mode voltage range of –4 to  
5 V in their SN65LVDS/T33 and SN65LVDS/T34.  
V
1A  
1
2
3
4
8
7
6
5
CC  
1A  
1Y  
2Y  
1B  
1Y  
2Y  
2A  
2B  
1B  
SN65LVDT9637B  
GND  
ONLY  
2A  
2B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

中文翻译

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SN65LVDS3486BD 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS3486AD TI

完全替代

 HIGH-SPEED DIFFERENTIAL RECEIVERS
AM26C32IDR TI

类似代替

 QUADRUPLE DIFFERENTIAL LINE RECEIVERS
AM26C31ID TI

类似代替

 QUADRUPLE DIFFERENTIAL LINE DRIVERS

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 		QUAD LINE TRANSCEIVER, PDSO16
SN65LVDS3486IDR TI

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