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SN65LVDS3486B PDF预览

SN65LVDS3486B

更新时间： 2024-11-17 23:03:07
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德州仪器 - TI /
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20页 293K
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HIGH-SPEED DIFFERENTIAL RECEIVERS

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SN65LVDS3486B 数据手册

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SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B  
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B  
HIGH-SPEED DIFFERENTIAL RECEIVERS  
SLLS440A – OCTOBER 2000 – REVISED MAY 2001  
SN65LVDS32B  
SN65LVDT32B  
Meets or Exceeds the Requirements of  
ANSI EIA/TIA-644 Standard for Signaling  
Rates up to 400 Mbps  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
†
Operates With a Single 3.3-V Supply  
G
G
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
–2-V to 4.4-V Common-Mode Input Voltage  
Range  
4B  
4A  
4Y  
G
SN65LVDT32B  
ONLY (4 Places)  
1A  
1Y  
Differential Input Thresholds <50 mV With  
50 mV of Hysteresis Over Entire  
Common-Mode Input Voltage Range  
1Y  
G
1B  
2Y  
2A  
11 3Y  
10 3A  
2A  
2B  
Integrated 110-Ω Line Termination  
Resistors Offered With the LVDT Series  
2B  
2Y  
3Y  
4Y  
9
GND  
3B  
Propagation Delay Times 4 ns (typ)  
3A  
3B  
4A  
4B  
Active Fail Safe Assures a High-Level  
Output With No Input  
Bus-Pin ESD Protection Exceeds  
15 kV HBM  
Inputs Remain High-Impedance on Power  
Down  
SN65LVDS3486B  
SN65LVDT3486B  
Recommended Maximum Parallel Rate of  
200 M-Transfers/s  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
Available in Small-Outline Package With  
1,27 mm Terminal Pitch  
SN65LVDT3486B  
1B  
1A  
V
CC  
4B  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
ONLY (4 Places)  
1A  
1B  
Pin-Compatible With the AM26LS32,  
MC3486, or µA9637  
1Y  
1Y  
4A  
1,2EN  
1,2EN  
2Y  
4Y  
description  
2A  
2B  
3,4EN  
2Y  
3Y  
4Y  
2A  
11 3Y  
10 3A  
This family of differential line receivers offers  
improved performance and features that imple-  
ment the electrical characteristics of low-voltage  
differential signaling (LVDS). LVDS is defined in  
the TIA/EIA-644 standard. This improved perfor-  
mance represents the second generation of  
receiver products for this standard, providing a  
better overall solution for the cabled environment.  
This generation of products is an extension to TI’s  
overall product portfolio and is not necessarily a  
replacement for older LVDS receivers.  
2B  
3A  
3B  
GND  
9
3B  
3,4EN  
4A  
4B  
SN65LVDS9637B  
SN65LVDT9637B  
D PACKAGE  
(TOP VIEW)  
Logic Diagram  
(positive logic)  
Improved features include an input common-  
mode voltage range 2 V wider than the minimum  
required by the standard. This will allow longer  
cable lengths by tripling the allowable ground  
noise tolerance to 3 V between a driver and  
receiver. TI has additionally introduced an even  
wider input common-mode voltage range of –4 to  
5 V in their SN65LVDS/T33 and SN65LVDS/T34.  
V
1A  
1
2
3
4
8
7
6
5
CC  
1A  
1Y  
2Y  
1B  
1Y  
2Y  
2A  
2B  
1B  
SN65LVDT9637B  
GND  
ONLY  
2A  
2B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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