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SN65LVDS2DBV PDF预览

SN65LVDS2DBV

更新时间： 2024-09-15 22:36:59
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
10页 133K
描述
HIGH-SPEED DIFFERENTIAL LINE RECEIVER

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SN65LVDS2DBV 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOT-23
包装说明：LSSOP, TSOP5/6,.11,37针数：5
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01风险等级：5.28
差分输出：NO驱动器位数：1
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE RECEIVER
接口标准：EIA-644-A; TIA-644-AJESD-30 代码：R-PDSO-G5
JESD-609代码：e4长度：2.9 mm
湿度敏感等级：1功能数量：1
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C最大输出低电流：0.008 A
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：TSOP5/6,.11,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：3.6 ns接收器位数：1
座面最大高度：1.45 mm子类别：Line Driver or Receivers
最大压摆率：8 mA最大供电电压：3.6 V
最小供电电压：2.4 V标称供电电压：3.3 V
表面贴装：YES技术：TTL
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：3.1 ns宽度：1.6 mm
Base Number Matches：1

SN65LVDS2DBV 数据手册

 浏览型号SN65LVDS2DBV的Datasheet PDF文件第2页浏览型号SN65LVDS2DBV的Datasheet PDF文件第3页浏览型号SN65LVDS2DBV的Datasheet PDF文件第4页浏览型号SN65LVDS2DBV的Datasheet PDF文件第5页浏览型号SN65LVDS2DBV的Datasheet PDF文件第6页浏览型号SN65LVDS2DBV的Datasheet PDF文件第7页 
SN65LVDS2  
HIGH-SPEED DIFFERENTIAL LINE RECEIVER  
SLLS406 – DECEMBER 1999  
SN65LVDS2  
DBV PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Meets or Exceeds ANSI TIA/EIA-644  
Standard  
Designed for Signaling Rates up to  
400 Mbps  
1
2
3
5
R
B
V
CC  
Operates From a 2.4-V to 3.6-V Supply  
Available in the SOT-23 Package  
GND  
A
Differential Input Voltage Threshold Less  
Than 100 mV  
4
D
Propagation Delay Times, 2.5 ns Typical  
logic diagram  
D
Power Dissipation at 200 MHz Is Typically  
60 mW  
3
A
B
5
D
D
D
Bus-Pin ESD Protection Exceeds 15 kV  
Open-Circuit Fail Safe  
R
4
Output is High Impedance With V  
< 1.5 V  
CC  
Function Table  
description  
INPUTS  
OUTPUT  
R
The SN65LVDS2 is a single low-voltage differen-  
tial line receiver in a small-outline transistor  
package. The inputs comply with the TIA/EIA-644  
standardandprovideamaximumdifferentialinput  
threshold of 100 mV over an input common-mode  
voltage range of 0 V to 2.4 V.  
V
= V – V  
A B  
ID  
V
≥ 100 mV  
H
?
L
H
ID  
–100 mV < V < 100 mV  
ID  
V
≤ –100 mV  
ID  
Open  
When used with a low-voltage differential  
signaling(LVDS)driver(suchastheSN65LVDS1)  
in a point-to-point or multidrop configuration; data  
H = high level, L = low level , ? = indeterminate  
or clocking signals can be transmitted over printed-circuit board traces or cables at very high rates with very  
low electromagnetic emissions and power consumption.  
The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the  
receiving-end of the cable or transmission media. TI offers you both the SN65LVDS2, which requires this  
external resistor, or its companion the SN65LVDT2, which eliminates the need by integrating it with the receiver.  
The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make these devices  
ideal for battery-powered applications.  
The SN65LVDS2 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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