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SN65LVDS180MPWREP

更新时间： 2024-11-24 12:15:03
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德州仪器 - TI 驱动器
页数 文件大小 规格书
22页 439K
描述
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

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SN65LVDS180MPWREP 数据手册

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SN65LVDS179-EP, SN65LVDS180-EP  
SN65LVDS050-EP, SN65LVDS051-EP  
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS  
www.ti.com  
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007  
FEATURES  
SN65LVDS179  
D OR DGK PACKAGE  
•
Controlled Baseline  
One Assembly/Test Site, One Fabrication  
Site  
(TOP VIEW)  
5
–
3
2
Y
Z
D
R
6
8
7
V
CC  
A
B
Z
Y
1
2
3
4
8
7
6
5
R
D
•
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
A
B
GND  
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
SN65LVDS180  
D OR PW PACKAGE  
(TOP VIEW)  
Meet or Exceed the Requirements of ANSI  
TIA/EIA-644-1995 Standard  
9
NC  
V
V
A
B
Z
Y
•
•
•
•
Signaling Rates up to 400 Mbps  
Bus-Terminal ESD Exceeds 12 kV  
Operates From a Single 3.3-V Supply  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
5
CC  
Y
Z
D
10  
R
RE  
CC  
4
3
DE  
RE  
DE  
D
12  
11  
Low-Voltage Differential Signaling With  
Typical Output Voltages of 350 mV and a  
100-Ω Load  
A
B
2
R
GND  
GND  
NC  
8
•
•
Propagation Delay Times  
SN65LVDS050  
–
–
Driver: 1.7 ns Typ  
14  
13  
D OR PW PACKAGE  
(TOP VIEW)  
15  
1Y  
1Z  
Receiver: 3.7 ns Typ  
1D  
12  
9
Power Dissipation at 200 MHz  
1B  
1A  
1R  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
DE  
2D  
10  
11  
2Y  
2Z  
–
–
Driver: 25 mW Typical  
1D  
1Y  
1Z  
DE  
2Z  
Receiver: 60 mW Typical  
RE  
2R  
2
1
•
•
LVTTL Input Levels Are 5-V Tolerant  
3
1A  
1B  
1R  
Receiver Maintains High Input Impedance  
With VCC < 1.5 V  
2A  
4
5
RE  
2R  
6
7
2B  
GND  
10 2Y  
2D  
2A  
2B  
•
Receiver Has Open-Circuit Fail Safe  
9
SN65LVDS051  
D OR PW PACKAGE  
(TOP VIEW)  
14  
15  
1Y  
1D  
13  
1Z  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
4
3
1DE  
1R  
2
1
1D  
1Y  
1A  
1B  
1R  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
1DE  
2R  
1Z  
2DE  
10  
11  
9
2Y  
2Z  
2D  
2A  
11 2Z  
12  
10  
9
2B  
GND  
2Y  
2D  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
2DE  
2R  
6
7
2A  
2B  
5
DESCRIPTION/ORDERING INFORMATION  
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and  
receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The  
TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of  
247 mV into a 100-Ω load, and receipt of 100-mV signals with up to 1 V of ground potential difference between  
a transmitter and receiver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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