5秒后页面跳转
捷配首页

Datasheet > SN65LVDS104PWLE
SN65LVDS104PWLE PDF预览

SN65LVDS104PWLE

更新时间： 2024-01-17 02:47:38
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
28页 750K
描述
LINE TRANSCEIVER, PDSO16, PLASTIC, TSSOP-16

阅读下载

中文翻译

获取价格

SN65LVDS104PWLE 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.43
差分输出：YES驱动器位数：4
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G16
长度：5 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
最大接收延迟：4.2 ns接收器位数：1
座面最大高度：1.2 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL最大传输延迟：4.2 ns
宽度：4.4 mmBase Number Matches：1

SN65LVDS104PWLE 数据手册

 浏览型号SN65LVDS104PWLE的Datasheet PDF文件第2页浏览型号SN65LVDS104PWLE的Datasheet PDF文件第3页浏览型号SN65LVDS104PWLE的Datasheet PDF文件第4页浏览型号SN65LVDS104PWLE的Datasheet PDF文件第5页浏览型号SN65LVDS104PWLE的Datasheet PDF文件第6页浏览型号SN65LVDS104PWLE的Datasheet PDF文件第7页 
SN65LVDS104  
SN65LVDS105  
www.ti.com  
SLLS396F–SEPTEMBER 1999–REVISED JANUARY 2005  
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS  
FEATURES  
SN65LVDS104  
D OR PW PACKAGE  
(Marked as LVDS104)  
(TOP VIEW)  
SN65LVDS105  
D OR PW PACKAGE  
(Marked as LVDS105)  
(TOP VIEW)  
•
Receiver and Drivers Meet or Exceed the  
Requirements of ANSI EIA/TIA-644 Standard  
– SN65LVDS105 Receives Low-Voltage TTL  
(LVTTL) Levels  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
– SN65LVDS104 Receives Differential Input  
Levels, ±100 mV  
V
CC  
V
CC  
•
Typical Data Signaling Rates to 400 Mbps or  
Clock Frequencies to 400 MHz  
GND  
A
GND  
A
11 3Z  
11 3Z  
•
•
Operates From a Single 3.3-V Supply  
10  
9
NC  
EN4  
4Y  
4Z  
10  
9
B
EN4  
4Y  
4Z  
Low-Voltage Differential Signaling With  
Typical Output Voltage of 350 mV and a 100-Ω  
Load  
logic diagram (positive logic)  
•
Propagation Delay Time  
’LVDS104  
– SN65LVDS105 – 2.2 ns (Typ)  
– SN65LVDS104 – 3.1 ns (Typ)  
LVTTL Levels Are 5-V Tolerant  
1Y  
1Z  
EN1  
EN2  
•
•
2Y  
2Z  
Electrically Compatible With LVDS, PECL,  
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,  
SSTL, or HSTL Outputs With External  
Networks  
EN3  
3Y  
3Z  
A
B
•
Driver Outputs Are High Impedance When  
Disabled or With VCC <1.5 V  
4Y  
4Z  
•
•
Bus-Pin ESD Protection Exceeds 16 kV  
SOIC and TSSOP Packaging  
EN4  
’LVDS105  
1Y  
DESCRIPTION  
1Z  
EN1  
EN2  
The SN65LVDS104 and SN65LVDS105 are a differ-  
ential line receiver and a LVTTL input (respectively)  
connected to four differential line drivers that im-  
plement the electrical characteristics of low-voltage  
differential signaling (LVDS). LVDS, as specified in  
EIA/TIA-644 is a data signaling technique that offers  
low-power, low-noise coupling, and switching speeds  
to transmit data at relatively long distances. (Note:  
The ultimate rate and distance of data transfer is  
dependent upon the attenuation characteristics of the  
media, the noise coupling to the environment, and  
other system characteristics.)  
2Y  
2Z  
EN3  
A
3Y  
3Z  
4Y  
4Z  
EN4  
The intended application of this device and signaling technique is for point-to-point baseband data transmission  
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board  
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse  
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.  
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...28

中文翻译

下载PDF

与SN65LVDS104PWLE相关器件

型号 品牌 获取价格 描述 数据表
SN65LVDS104PWR TI

获取价格

 		4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS104PWRG4 TI

获取价格

 		4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS105 TI

获取价格

 		4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS1050 TI

获取价格

 		HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SN65LVDS1050PW TI

获取价格

 		HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SN65LVDS1050PWG4 TI

获取价格

 		双路 LVDS 收发器 | PW | 16 | -40 to 85
SN65LVDS1050PWR TI

获取价格

 		Dual LVDS Transceiver 16-TSSOP -40 to 85
SN65LVDS1050PWRG4 TI

获取价格

 		DUAL LINE TRANSCEIVER, PDSO16, GREEN, PLASTIC, TSSOP-16
SN65LVDS105D TI

获取价格

 		4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS105DG4 TI

获取价格

 		4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

与SN65LVDS104PWLE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证