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SN65LVDS104PW PDF预览

SN65LVDS104PW

更新时间： 2024-02-22 21:27:17
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路中继器光电二极管PC
页数 文件大小 规格书
20页 279K
描述
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

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中文翻译

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SN65LVDS104PW 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.27Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：4666
Samacsys Pin Count：16Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：d(r-pdso-g16)
Samacsys Released Date：2015-04-16 09:48:08Is Samacsys：N
差分输出：YES驱动器位数：4
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE TRANSCEIVER
接口标准：EIA-644; TIA-644JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：2 V
输出特性：DIFFERENTIAL最大输出低电流：0.00002 A
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：4.2 ns
接收器位数：1座面最大高度：1.2 mm
子类别：Line Driver or Receivers最大压摆率：35 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：4.2 ns宽度：4.4 mm
Base Number Matches：1

SN65LVDS104PW 数据手册

 浏览型号SN65LVDS104PW的Datasheet PDF文件第2页浏览型号SN65LVDS104PW的Datasheet PDF文件第3页浏览型号SN65LVDS104PW的Datasheet PDF文件第4页浏览型号SN65LVDS104PW的Datasheet PDF文件第5页浏览型号SN65LVDS104PW的Datasheet PDF文件第6页浏览型号SN65LVDS104PW的Datasheet PDF文件第7页 
SN65LVDS104, SN65LVDS105  
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS  
SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999  
Receiver and Drivers Meet or Exceed the  
Requirements of ANSI EIA/TIA-644  
Standard  
SN65LVDS104  
D OR PW PACKAGE  
(TOP VIEW)  
SN65LVDS105  
D OR PW PACKAGE  
(TOP VIEW)  
– SN65LVDS105 Receives Low-Voltage TTL  
(LVTTL) Levels  
– SN65LVDS104 Receives Differential Input  
Levels, ±100 mV  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
3Z  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
3Z  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
V
V
CC  
CC  
Designed for Signaling Rates up to  
630 Mbps  
GND  
A
GND  
A
Operates From a Single 3.3-V Supply  
B
10 4Y  
4Z  
NC  
EN4  
10 4Y  
4Z  
EN4  
9
9
Low-Voltage Differential Signaling With  
Typical Output Voltage of 350 mV and a  
100-Ω Load  
Propagation Delay Time  
logic diagram (positive logic)  
– SN65LVDS105 . . . 2.2 ns (Typ)  
– SN65LVDS104 . . . 3.1 ns (Typ)  
’LVDS104  
1Y  
Electrically Compatible With LVDS, PECL,  
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,  
SSTL, or HSTL Outputs With External  
Networks  
1Z  
EN1  
EN2  
2Y  
2Z  
EN3  
Driver Outputs Are High Impedance When  
3Y  
3Z  
Disabled or With V  
<1.5 V  
CC  
A
B
Bus-Pin ESD Protection Exceeds 16 kV  
SOIC and TSSOP Packaging  
4Y  
4Z  
EN4  
description  
’LVDS105  
The SN65LVDS104 and SN65LVDS105 are a  
differential line receiver and a LVTTL input  
(respectively) connected to four differential line  
drivers that implement the electrical characteris-  
tics of low-voltage differential signaling (LVDS).  
LVDS, as specified in EIA/TIA-644 is a data  
signaling technique that offers low-power, low-  
noise coupling, and switching speeds to transmit  
data at speeds up to 655 Mbps at relatively long  
distances. (Note: The ultimate rate and distance  
of data transfer is dependent upon the attenuation  
characteristics of the media, the noise coupling to  
the environment, and other system characteris-  
tics.)  
1Y  
1Z  
EN1  
EN2  
2Y  
2Z  
EN3  
A
3Y  
3Z  
4Y  
4Z  
EN4  
The intended application of this device and signaling technique is for point-to-point baseband data transmission  
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board  
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse  
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.  
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.  
The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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SN65LVDS104PW 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS104PWR TI

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SN65LVDS104PWG4 TI

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SN65LVDS104PWRG4 TI

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SN65LVDS1050PWR TI

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