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SN65LVDS104DRG4 PDF预览

SN65LVDS104DRG4

更新时间： 2024-01-23 12:21:35
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路中继器光电二极管
页数 文件大小 规格书
24页 415K
描述
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

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中文翻译

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SN65LVDS104DRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.26Is Samacsys：N
差分输出：YES驱动器位数：4
高电平输入电流最大值：0.00002 A输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE TRANSCEIVER接口标准：EIA-644; TIA-644
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
最小输出摆幅：2 V输出特性：DIFFERENTIAL
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：4.2 ns
接收器位数：1座面最大高度：1.75 mm
子类别：Line Driver or Receivers最大压摆率：35 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：3.6 V
电源电压1-分钟：3 V电源电压1-Nom：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
最大传输延迟：4.2 ns宽度：3.9 mm
Base Number Matches：1

SN65LVDS104DRG4 数据手册

 浏览型号SN65LVDS104DRG4的Datasheet PDF文件第2页浏览型号SN65LVDS104DRG4的Datasheet PDF文件第3页浏览型号SN65LVDS104DRG4的Datasheet PDF文件第4页浏览型号SN65LVDS104DRG4的Datasheet PDF文件第5页浏览型号SN65LVDS104DRG4的Datasheet PDF文件第6页浏览型号SN65LVDS104DRG4的Datasheet PDF文件第7页 
SN65LVDS104  
SN65LVDS105  
www.ti.com  
SLLS396F–SEPTEMBER 1999–REVISED JANUARY 2005  
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS  
FEATURES  
SN65LVDS104  
D OR PW PACKAGE  
(Marked as LVDS104)  
(TOP VIEW)  
SN65LVDS105  
D OR PW PACKAGE  
(Marked as LVDS105)  
(TOP VIEW)  
•
Receiver and Drivers Meet or Exceed the  
Requirements of ANSI EIA/TIA-644 Standard  
– SN65LVDS105 Receives Low-Voltage TTL  
(LVTTL) Levels  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
EN1  
EN2  
EN3  
1Y  
1Z  
2Y  
2Z  
3Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
– SN65LVDS104 Receives Differential Input  
Levels, ±100 mV  
V
CC  
V
CC  
•
Typical Data Signaling Rates to 400 Mbps or  
Clock Frequencies to 400 MHz  
GND  
A
GND  
A
11 3Z  
11 3Z  
•
•
Operates From a Single 3.3-V Supply  
10  
9
NC  
EN4  
4Y  
4Z  
10  
9
B
EN4  
4Y  
4Z  
Low-Voltage Differential Signaling With  
Typical Output Voltage of 350 mV and a 100-Ω  
Load  
logic diagram (positive logic)  
•
Propagation Delay Time  
’LVDS104  
– SN65LVDS105 – 2.2 ns (Typ)  
– SN65LVDS104 – 3.1 ns (Typ)  
LVTTL Levels Are 5-V Tolerant  
1Y  
1Z  
EN1  
EN2  
•
•
2Y  
2Z  
Electrically Compatible With LVDS, PECL,  
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,  
SSTL, or HSTL Outputs With External  
Networks  
EN3  
3Y  
3Z  
A
B
•
Driver Outputs Are High Impedance When  
Disabled or With VCC <1.5 V  
4Y  
4Z  
•
•
Bus-Pin ESD Protection Exceeds 16 kV  
SOIC and TSSOP Packaging  
EN4  
’LVDS105  
1Y  
DESCRIPTION  
1Z  
EN1  
EN2  
The SN65LVDS104 and SN65LVDS105 are a differ-  
ential line receiver and a LVTTL input (respectively)  
connected to four differential line drivers that im-  
plement the electrical characteristics of low-voltage  
differential signaling (LVDS). LVDS, as specified in  
EIA/TIA-644 is a data signaling technique that offers  
low-power, low-noise coupling, and switching speeds  
to transmit data at relatively long distances. (Note:  
The ultimate rate and distance of data transfer is  
dependent upon the attenuation characteristics of the  
media, the noise coupling to the environment, and  
other system characteristics.)  
2Y  
2Z  
EN3  
A
3Y  
3Z  
4Y  
4Z  
EN4  
The intended application of this device and signaling technique is for point-to-point baseband data transmission  
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board  
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse  
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.  
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN65LVDS104DRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS104DG4 TI

完全替代

 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS104D TI

完全替代

 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
SN65LVDS104DR TI

类似代替

 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

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SN65LVDS104PWG4 TI

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SN65LVDS104PWRG4 TI

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SN65LVDS105 TI

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SN65LVDS1050 TI

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SN65LVDS1050PWG4 TI

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 		双路 LVDS 收发器 | PW | 16 | -40 to 85
SN65LVDS1050PWR TI

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 		Dual LVDS Transceiver 16-TSSOP -40 to 85

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