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SN65LVDS101D

更新时间： 2024-11-25 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 中继器
页数 文件大小 规格书
25页 1062K
描述
DIFFERENTIAL TRANSLATOR/REPEATER

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SN65LVDS101D 数据手册

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SN65LVDS100, SN65LVDT100  
SN65LVDS101, SN65LVDT101  
www.ti.com  
SLLS516C–AUGUST 2002–REVISED JUNE 2004  
DIFFERENTIAL TRANSLATOR/REPEATER  
FEATURES  
DESCRIPTION  
•
•
•
•
•
Designed for Signaling Rates (1) ≥ 2 Gbps  
Total Jitter < 65 ps  
The SN65LVDS100, SN65LVDT100, SN65LVDS101,  
and SN65LVDT101 are a high-speed differential re-  
ceiver and driver connected as a repeater. The  
receiver accepts low-voltage differential signaling  
(LVDS), positive-emitter-coupled logic (PECL), or cur-  
rent-mode logic (CML) input signals at rates up to 2  
Gbps and repeats it as either an LVDS or PECL  
output signal. The signal path through the device is  
differential for low radiated emissions and minimal  
added jitter.  
Low-Power Alternative for the MC100EP16  
Low 100 ps (Max) Part-To-Part Skew  
25 mV of Receiver Input Threshold Hysteresis  
Over 0-V to 4-V Common-Mode Range  
•
Inputs Electrically Compatible With LVPECL,  
CML, and LVDS Signal Levels  
•
•
•
3.3-V Supply Operation  
The  
outputs  
of  
the  
SN65LVDS100  
and  
LVDT Integrates 110-Ω Terminating Resistor  
Offered in SOIC and MSOP  
SN65LVDT100 are LVDS levels as defined by  
TIA/EIA-644-A. The outputs of the SN65LVDS101  
and SN65LVDT101 are compatible with 3.3-V PECL  
levels. Both drive differential transmission lines with  
nominally 100-Ω characteristic impedance.  
APPLICATIONS  
•
•
•
•
•
622 MHz Central Office Clock Distribution  
High-Speed Network Routing  
Wireless Basestations  
Low Jitter Clock Repeater  
Serdes LVPECL Output to FPGA LVDS  
Input Translator  
The SN65LVDT100 and SN65LVDT101 include a  
110-Ω differential line termination resistor for less  
board space, fewer components, and the shortest  
stub length possible. They do not include the VBB  
voltage reference found in the SN65LVDS100 and  
SN65LVDS101. VBB provides a voltage reference of  
typically 1.35 V below VCC for use in receiving  
single-ended input signals and is particularly useful  
with single-ended 3.3-V PECL inputs. When not used,  
VBB should be unconnected or open.  
(1) The signaling rate of a line is the number of voltage  
transitions that are made per second expressed in the units  
bps (bits per second).  
All devices are characterized for operation from  
–40°C to 85°C.  
FUNCTIONAL DIAGRAM  
EYE PATTERN  
SN65LVDS100 and SN65LVDS101  
8
2
4
2 Gbps  
- 1 PRBS  
V
V
BB  
CC  
23  
2
A
7
6
Y
V
= 3.3 V  
CC  
V
= 200 mV  
ID  
Z
V
IC  
= 1.2 V  
3
B
Vert.Scale= 200 mV/div  
SN65LVDT100 and SN65LVDT101  
1 GHz  
2
A
7
Y
Z
110 Ω  
6
3
B
Horizontal Scale= 200 ps/div  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains PRO-  
Copyright © 2002–2004, Texas Instruments Incorporated  
DUCTION DATA information current as of publication date. Prod-  
ucts conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily  
include testing of all parameters.  
1234567...25

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SN65LVDS101D 替代型号

型号 品牌 替代类型 描述 数据表
SN65LVDS100DR TI

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SN65LVDT101D TI

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