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SN65LVDS050 PDF预览

SN65LVDS050

更新时间： 2024-11-17 22:36:59
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德州仪器 - TI 驱动器
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19页 261K
描述
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

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SN65LVDS050 数据手册

 浏览型号SN65LVDS050的Datasheet PDF文件第2页浏览型号SN65LVDS050的Datasheet PDF文件第3页浏览型号SN65LVDS050的Datasheet PDF文件第4页浏览型号SN65LVDS050的Datasheet PDF文件第5页浏览型号SN65LVDS050的Datasheet PDF文件第6页浏览型号SN65LVDS050的Datasheet PDF文件第7页 
SN65LVDS179, SN65LVDS180, SN65LVDS050, SN65LVDS051  
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS  
SLLS301G – APRIL 1998 – REVISED MARCH 2000  
Meets or Exceeds the Requirements of  
SN65LVDS179D (Marked as DL179 or LVD179)  
SN65LVDS179DGK (Marked as S79)  
(TOP VIEW)  
ANSI TIA/EIA-644-1995 Standard  
Signaling Rates up to 400 Mbit/s  
Bus-Terminal ESD Exceeds 12 kV  
Operates from a Single 3.3-V Supply  
5
6
8
7
3
Y
Z
D
R
V
A
B
Z
Y
1
2
3
4
8
7
6
5
CC  
R
A
B
2
Low-Voltage Differential Signaling With  
Typical Output Voltages of 350 mV and a  
100 Ω Load  
D
GND  
Propagation Delay Times  
– Driver: 1.7 ns Typ  
SN65LVDS180D (Marked as LVDS180)  
(TOP VIEW)  
– Receiver: 3.7 ns Typ  
9
NC  
R
V
V
A
B
Z
Y
Power Dissipation at 200 MHz  
– Driver: 25 mW Typical  
– Receiver: 60 mW Typical  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
5
CC  
CC  
Y
Z
D
10  
4
3
RE  
DE  
RE  
DE  
LVTTL Input Levels are 5 V Tolerant  
12  
11  
A
B
D
2
Driver is High Impedance When Disabled or  
R
GND  
GND  
With V  
< 1.5 V  
CC  
NC  
8
Receiver has Open-Circuit Fail Safe  
Surface-Mount Packaging  
– D Package (SOIC)  
– DGK Package (MSOP) (’LVDS79 Only)  
14  
13  
SN65LVDS050D (Marked as LVDS050)  
15  
1Y  
1Z  
(TOP VIEW)  
1D  
12  
9
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
DE  
2D  
10  
11  
2Y  
2Z  
description  
1D  
1Y  
1Z  
DE  
1R  
The  
SN65LVDS179,  
SN65LVDS180,  
RE  
2R  
2
1
SN65LVDS050, and SN65LVDS051 are differen-  
tial line drivers and receivers that use low-voltage  
differential signaling (LVDS) to achieve signaling  
rates as high as 400 Mbps. The TIA/EIA-644  
standard compliant electrical interface provides a  
minimum differential output voltage magnitude of  
247 mV into a 100 Ω load and receipt of 100 mV  
signals with up to 1 V of ground potential  
difference between a transmitter and receiver.  
3
1A  
1B  
1R  
2A  
11 2Z  
10 2Y  
4
5
RE  
2R  
6
7
2B  
2A  
2B  
GND  
9
2D  
SN65LVDS051D (Marked as LVDS051)  
14  
13  
(TOP VIEW)  
15  
1Y  
1Z  
1D  
1B  
1A  
V
CC  
1D  
1Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
4
3
The intended application of this device and  
signaling technique is for point-to-point baseband  
data transmission over controlled impedance  
media of approximately 100 Ω characteristic  
impedance. The transmission media may be  
printed-circuit board traces, backplanes, or  
cables. (Note: The ultimate rate and distance of  
data transfer is dependent upon the attenuation  
characteristics of the media, the noise coupling to  
the environment, and other application specific  
characteristics).  
1DE  
1R  
2
1
1A  
1B  
1R  
1DE  
2R  
1Z  
10  
11  
2DE  
9
2Y  
2Z  
2D  
2A  
11 2Z  
10 2Y  
12  
5
2B  
2DE  
2R  
6
7
GND  
9
2D  
2A  
2B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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