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SN65LVDM050QDRG4Q1 PDF预览

SN65LVDM050QDRG4Q1

更新时间: 2024-11-19 11:06:55
品牌 Logo 应用领域
德州仪器 - TI 驱动线路驱动器或接收器驱动程序和接口
页数 文件大小 规格书
20页 279K
描述
汽车类双路 LVDS 收发器 | D | 16 | -40 to 125

SN65LVDM050QDRG4Q1 数据手册

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SN65LVDM050-Q1, SN65LVDM051-Q1  
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS  
SGLS128 – JULY 2002  
SN65LVDM050QDQ1 (Marked as LVDM050Q)  
Qualification in Accordance With  
AEC-Q100  
(TOP VIEW)  
14  
13  
15  
1Y  
1Z  
1D  
Qualified for Automotive Applications  
1B  
1A  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
12  
9
1D  
1Y  
1Z  
DE  
2Z  
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
DE  
2D  
10  
11  
2Y  
2Z  
1R  
RE  
2R  
2
1
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
1A  
1B  
2A  
1R  
2B  
10 2Y  
2D  
4
5
RE  
2R  
GND  
9
6
7
Low-Voltage Differential 50-Line Drivers  
and Receivers  
2A  
2B  
Signaling Rates up to 500 Mbps  
Bus-Terminal ESD Exceeds 12 kV  
Operates From a Single 3.3 V Supply  
SN65LVDM051QDQ1 (Marked as LVDM051Q)  
(TOP VIEW)  
14  
13  
15  
1Y  
1Z  
Low-Voltage Differential Signaling With  
Typical Output Voltages of 340 mV With a  
50-Load  
1D  
1B  
1A  
V
CC  
1D  
1Y  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
4
3
1DE  
1R  
2
1
1A  
1B  
1R  
Valid Output With as Little as 50-mV Input  
Voltage Difference  
1DE  
2R  
1Z  
2DE  
2Z  
10  
11  
9
2Y  
2Z  
Propagation Delay Times  
– Driver: 1.7 ns Typ  
– Receiver: 3.7 ns Typ  
2A  
2D  
2B  
10 2Y  
2D  
12  
5
2DE  
2R  
6
7
GND  
9
2A  
2B  
Power Dissipation at 200 MHz  
– Driver: 50 mW Typical  
– Receiver: 60 mW Typical  
LVTTL Input Levels Are 5 V Tolerant  
Driver Is High Impedance When Disabled or  
With V  
< 1.5 V  
CC  
Receiver Has Open-Circuit Fail Safe  
Contact factory for details. Q100 qualification data available on  
request.  
description  
The SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage  
differential signaling (LVDS) to achieve signaling rates as high as 500 Mbps (per TIA/EIA-644 definition). These  
circuitsaresimilartoTIA/EIA-644standardcompliantdevices(SN65LVDS)counterparts, exceptthattheoutput  
current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude  
of 247 mV across a 50-load simulating two transmission lines in parallel. This allows having data buses with  
more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV  
with up to 1 V of ground potential difference between a transmitter and receiver.  
The intended application of these devices and signaling techniques is point-to-point and multipoint, baseband  
data transmission over a controlled impedance media of approximately 100 of characteristic impedance. The  
transmission media may be printed-circuit board traces, backplanes, or cables.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002 Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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