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SN65LV1023DB PDF预览

SN65LV1023DB

更新时间: 2024-11-19 22:33:59
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
20页 290K
描述
30 MHZ TO 66MHZ 10:1 LVDS SERIALIZER/DESERIALIZER

SN65LV1023DB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP28,.3针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.45
差分输出:YES驱动器位数:1
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:GENERAL PURPOSEJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:10.2 mm
湿度敏感等级:1功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP28,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:2 mm子类别:Line Driver or Receivers
最大压摆率:70 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:0.4 ns宽度:5.3 mm
Base Number Matches:1

SN65LV1023DB 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢀ ꢁꢂ ꢃꢄꢅ ꢆꢈ ꢈꢋ  
ꢉ ꢇꢌꢍ ꢎꢏ ꢐ ꢑ ꢂ ꢂ ꢌꢍꢎ ꢏꢒ ꢆ ꢇ ꢓꢆ ꢄꢅꢔꢀ ꢀꢕ ꢖꢗꢘ ꢄꢗ ꢙꢕ ꢖꢊ ꢔꢕꢀꢕ ꢖꢗ ꢘ ꢄꢗ ꢙꢕ ꢖ  
SLLS527G − FEBRUARY 2002 − REVISED JANUARY 2005  
D
300-Mbps to 660-Mbps Serial LVDS Data  
Payload Bandwidth at 30-MHz to 66-MHz  
System Clock  
D
D
D
D
Lock Indicator  
No External Components Required for PLL  
Low-Cost 28-Pin SSOP Package  
Industrial Temperature Qualified,  
D
D
D
Pin-Compatible Superset of NSM  
DS92LV1023/DS92LV1224  
T = 40°C to 85°C  
A
Chipset (Serializer/Deserializer) Power  
Consumption <450 mW (Typ) at 66 MHz  
D
Programmable Edge Trigger on Clock  
D
Flow-Through Pinout for Easy PCB Layout  
Synchronization Mode for Faster Lock  
SN65LV1023  
Serializer  
SN65LV1224  
Deserializer  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
SYNC1  
SYNC2  
DV  
DV  
AV  
AGND  
PWRDN  
AGND  
AGND  
RCLK_R/F  
REFCLK  
R
R
R
R
R
CC  
CC  
CC  
OUT0  
OUT1  
OUT2  
OUT3  
OUT4  
2
2
3
3
D
D
D
D
D
D
D
D
D
D
IN0  
IN1  
IN2  
IN3  
IN4  
IN5  
IN6  
IN7  
IN8  
IN9  
4
4
AV  
CC  
5
5
R +  
I
6
6
R −  
DV  
DGND  
DV  
I
CC  
7
7
D +  
PWRDN  
REN  
RCLK  
LOCK  
O
8
8
D −  
O
CC  
9
9
AGND  
DEN  
AGND  
DGND  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
R
R
R
R
R
OUT5  
OUT6  
OUT7  
OUT8  
OUT9  
AV  
CC  
AV  
AGND  
AGND  
DGND  
CC  
TCLK_R/F  
TCLK  
DGND  
DGND  
description  
The SN65LV1023 serializer and SN65LV1224 deserializer comprise a 10-bit serdes chipset designed to  
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 30 MHz  
to 66 MHz. Including overhead, this translates into a serial data rate between 360-Mbps and 792-Mbps payload  
encoded throughput.  
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC  
patterns, or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,  
the deserializer establishes lock within specified, shorter time parameters.  
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is  
available to place the output pins in the high-impedance state without losing PLL lock.  
The SN65LV1023 and SN65LV1224 are characterized for operation over ambient air temperature of 40°C to  
85°C.  
ORDERING INFORMATION  
DEVICE  
Serializer  
PART NUMBER  
SN65LV1023DB  
SN65LV1224DB  
Deserializer  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢐꢨ  
Copyright 2002 − 2005, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN65LV1023DB 替代型号

型号 品牌 替代类型 描述 数据表
DS92LV1021TMSA/NOPB TI

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16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

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