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SLLS376C− MAY 2000 − REVISED DECEMBER 2000
SN65LBC176AQD (Marked as B176AQ)
SN65LBC176AD (Marked as BL176A)
SN65LBC176AP (Marked as 65LBC176A)
SN75LBC176AD (Marked as LB176A)
SN75LBC176AP (Marked as 75LBC176A)
(TOP VIEW)
D
High-Speed Low-Power LinBiCMOS
Circuitry Designed for Signaling Rates Up
to 30 Mbps
†
D
D
Bus-Pin ESD Protection Exceeds 12 kV
HBM
Compatible With ANSI Standard
TIA/EIA-485-A and ISO 8482:1987(E)
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
CC
D
Low Skew
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
GND
D
D
Very Low Disabled Supply-Current
Requirements . . . 700 µA Maximum
Common Mode Voltage Range of −7 V
to 12 V
logic diagram (positive logic)
3
DE
D
Thermal-Shutdown Protection
4
2
1
D
Driver Positive and Negative Current
Limiting
D
RE
R
6
7
D
D
D
D
Open-Circuit Fail-Safe Receiver Design
Receiver Input Sensitivity . . . 200 mV Max
Receiver Input Hysteresis . . . 50 mV Typ
A
B
Bus
Function Tables
Glitch-Free Power-Up and Power-Down
Protection
DRIVER
D
Available in Q-Temp Automotive
INPUT
D
H
L
X
ENABLE
OUTPUTS
High Reliability Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards
DE
H
H
L
H
A
H
L
B
L
H
Z
L
Z
H
Open
description
The SN65LBC176A, SN65LBC176AQ, and
RECEIVER
SN75LBC176A differential bus transceivers are
monolithic, integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. They are designed for
balanced transmission lines and are compatible
with ANSI standard TIA/EIA-485-A and ISO 8482.
The A version offers improved switching perfor-
mance over its predecessors without sacrificing
significantly more power.
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
V
A
−V
RE
L
L
L
H
L
R
H
?
L
Z
H
B
V
ID
≥ 0.2 V
−0.2 V < V < 0.2 V
ID
V
ID
≤ −0.2 V
X
Open
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved
without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS and LinASIC are trademarks of Texas Instruments.
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Copyright 2000, Texas Instruments Incorporated
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1
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