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SN65LBC174ADWR PDF预览

SN65LBC174ADWR

更新时间: 2024-10-31 04:51:15
品牌 Logo 应用领域
德州仪器 - TI 线路驱动器或接收器驱动程序和接口接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
19页 480K
描述
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS

SN65LBC174ADWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:8 weeks
风险等级:5.11Is Samacsys:N
差分输出:YES驱动器位数:4
输入特性:STANDARD接口集成电路类型:LINE DRIVER
接口标准:EIA-422; TIA-422; EIA-485; TIA-485; ISO 8482JESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
湿度敏感等级:1功能数量:4
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C最小输出摆幅:1 V
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大接收延迟:座面最大高度:2.65 mm
子类别:Line Driver or Receivers最大压摆率:23 mA
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V电源电压1-最大:5.25 V
电源电压1-分钟:4.75 V电源电压1-Nom:5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
最大传输延迟:11 ns宽度:7.5 mm
Base Number Matches:1

SN65LBC174ADWR 数据手册

 浏览型号SN65LBC174ADWR的Datasheet PDF文件第2页浏览型号SN65LBC174ADWR的Datasheet PDF文件第3页浏览型号SN65LBC174ADWR的Datasheet PDF文件第4页浏览型号SN65LBC174ADWR的Datasheet PDF文件第5页浏览型号SN65LBC174ADWR的Datasheet PDF文件第6页浏览型号SN65LBC174ADWR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢈ ꢉ ꢊꢋ ꢀꢁꢈ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ  
ꢌ ꢍꢊꢎꢏ ꢍꢐꢄ ꢑ ꢏꢀꢒ ꢉꢓ ꢃ ꢎꢔ ꢕꢕ ꢑꢏ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢎ ꢏꢔ ꢗ ꢑꢏ ꢀ  
SLLS446C − OCTOBER 2000 − REVISED MAY 2003  
D
D
D
D
Designed for TIA/EIA-485, TIA/EIA-422 and  
ISO 8482 Applications  
D
D
Driver Positive- and Negative-Current  
Limiting  
Signaling Rates up to 30 Mbps  
Power-Up and Power-Down Glitch-Free for  
Line Insertion Applications  
Propagation Delay Times < 11 ns  
D
Thermal Shutdown Protection  
Low Standby Power Consumption  
1.5 mA Max  
D
Industry Standard Pin-Out, Compatible  
With SN75174, MC3487, DS96174, LTC487,  
and MAX3042  
D
Output ESD Protection Exceeds 13 kV  
description  
The SN65LBC174A and SN75LBC174A are quadruple differential line drivers with 3-state outputs, designed  
for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.  
These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits  
per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate  
rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise  
coupling to the environment.  
N PACKAGE  
(TOP VIEW)  
16-DW PACKAGE  
(TOP VIEW)  
logic diagram (positive logic)  
2
1Y  
1
2
3
4
5
6
7
8
16  
1
4
7
1A  
1Y  
1Z  
V
CC  
4A  
4Y  
4Z  
3,4EN  
3Z  
3Y  
1A  
1Y  
V
CC  
4A  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
1A  
1,2EN  
2A  
3
15  
14  
13  
12  
11  
10  
9
1Z  
1Z  
4Y  
6
5
2Y  
2Z  
1,2EN  
2Z  
2Y  
2A  
GND  
1,2EN  
2Z  
4Z  
3,4EN  
2Y  
11 3Z  
10 3Y  
10  
11  
3Y  
3Z  
9
2A  
3A  
3,4EN  
4A  
3A  
GND  
9
3A  
12  
15  
14  
13  
4Y  
4Z  
20-DW PACKAGE  
(TOP VIEW)  
logic diagram (positive logic)  
2
1
2
3
4
5
6
7
8
9
10  
20  
1A  
1Y  
NC  
1Z  
V
CC  
4A  
4Y  
NC  
4Z  
3,4EN  
3Z  
NC  
3Y  
1Y  
1
1A  
19  
18  
17  
16  
15  
14  
13  
12  
11  
4
1Z  
5
1,2EN  
8
2Y  
9
2A  
1,2EN  
2Z  
NC  
2Y  
2A  
GND  
6
2Z  
12  
3Y  
11  
3A  
14  
3Z  
15  
3,4EN  
3A  
18  
4Y  
19  
4A  
16  
4Z  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).  
ꢖꢤ  
Copyright 2001 − 20003, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN65LBC174ADWR 替代型号

型号 品牌 替代类型 描述 数据表
SN65LBC174ADW TI

完全替代

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QUAD LINE DRIVER, PDIP16, ROHS COMPLIANT, PLASTIC, DIP-16