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SGLS356 − MAY 2006
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D
D
Low-Current SN65HVD230M Standby Mode
FEATURES
370 µA Typical
Designed for Signaling Rates Up To
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
‡
1 Megabit/Second (Mbps)
D
Thermal Shutdown Protection
Open-Circuit Fail-Safe Design
D
D
D
D
D
D
Extended Temperature Performance of −55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature cycle,
autoclave or unbiased HAST, electromigration, bond intermetallic
life, and mold compound life. Such qualification testing should not
be viewed as justifying use of this component beyond specified
performance and environmental limits.
Enhanced Product-Change Notification
†
Qualification Pedigree
Operates With a 3.3-V Supply
Low Power Replacement for the PCA82C250
Footprint
SN65HVD230MD
(TOP VIEW)
D
Bus/Pin ESD Protection Exceeds 15-kV HBM
D
R
D
Controlled Driver Output Transition Times for
Improved Signal Quality on the
SN65HVD230M
1
2
3
4
8
7
6
5
S
GND
CANH
CANL
V
CC
R
V
D
D
Unpowered Node Does Not Disturb the Bus
ref
Compatible With the Requirements of the
ISO 11898 Standard
logic diagram (positive logic)
SN65HVD230M
Logic Diagram (Positive Logic)
3
5
V
V
ref
CC
D
1
8
R
S
7
6
CANH
CANL
4
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
‡
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
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Copyright 2006, Texas Instruments Incorporated
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1
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