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SN65555

更新时间: 2024-11-29 04:31:23
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德州仪器 - TI 驱动
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9页 211K
描述
ELECTROLUMINESCENT COLUMIN DRIVERS

SN65555 数据手册

 浏览型号SN65555的Datasheet PDF文件第2页浏览型号SN65555的Datasheet PDF文件第3页浏览型号SN65555的Datasheet PDF文件第4页浏览型号SN65555的Datasheet PDF文件第5页浏览型号SN65555的Datasheet PDF文件第6页浏览型号SN65555的Datasheet PDF文件第7页 
SLDS031A APRIL 1985 REVISED APRIL 1993  
SN75555 . . . N PACKAGE  
(TOP VIEW)  
Each Device Drives 32 Electrodes  
90-V Output Voltage Swing Capability  
Using Ramped Supply  
Q17  
Q16  
Q18  
Q19  
Q20  
Q21  
Q22  
1
40  
39  
38  
37  
36  
15-mA Output Source and Sink Current  
Capability  
2
Q15  
3
High-Speed Serially-Shifted Data Input  
Totem-Pole Outputs  
Q14  
4
Q13  
5
Q12  
6
35 Q23  
Latches on All Driver Outputs  
7
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
Q11  
Q24  
8
Q10  
Q25  
description  
9
Q9  
Q26  
The SN65555, SN75555, SN65556, and  
SN75556 are monolithic BIDFETintegrated  
circuits designed to drive the column electrodes of  
an electroluminescent display. The SN65556 and  
SN75556 output sequence is reversed from the  
SN65555 and SN75555 for ease in printed-circuit-  
board layout.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Q8  
Q27  
Q7  
Q28  
Q6  
Q29  
Q5  
Q30  
Q4  
Q31  
Q3  
Q32  
Q2  
OUTPUT ENABLE  
DATA IN  
Q1  
The devices consist of a 32-bit shift register, 32  
latches, and 32 output AND gates. Serial data is  
entered into the shift register on the low-to-high  
transition of CLOCK. When high, LATCHENABLE  
transfers the shift register contents to the outputs  
of the 32 latches. When OUTPUT ENABLE is  
high, all Q outputs are enabled. Data must be  
loaded into the latches and OUTPUT ENABLE  
SERIAL OUT  
CLOCK  
GND  
LATCH ENABLE  
V
V
CC1  
CC2  
SN65555, SN75555 . . . FN PACKAGE  
(TOP VIEW)  
must be high before supply voltage V  
ramped up.  
is  
CC2  
6
5
4
3
2
1 44 43 42 41 40  
39  
Q23  
Q24  
Q25  
Q26  
Q27  
Q28  
Q29  
Q11  
Q10  
Q9  
Q8  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
7
Serial data output from the shift register can be  
used to cascade shift registers. This output is not  
affected by LATCH ENABLE or OUTPUT  
ENABLE.  
8
38  
37  
36  
35  
34  
33  
9
10  
11  
12  
13  
14  
15  
16  
17  
The SN65555 and SN65556 are characterized for  
operation from 40 C to 85 C. The SN75555 and  
SN75556 are characterized for operation from  
0 C to 70 C.  
32 Q30  
31 Q31  
30  
Q32  
NC  
29  
18 19 20 21 22 23 24 25 26 27 28  
NC No internal connection  
BIDFET Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.  
Copyright 1993, Texas Instruments Incorporated  
41  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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