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SN65220_07 PDF预览

SN65220_07

更新时间: 2024-11-14 04:31:23
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德州仪器 - TI /
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描述
USB PORT TRANSIENT SUPPERSSORS

SN65220_07 数据手册

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ꢁꢂ  
ꢁꢂ  
ꢁꢇ  
www.ti.com  
SLLS266F − FEBRUARY 1997 − REVISED JULY 2004  
FEATURES  
APPLICATIONS  
D
D
Design to Protect Submicron 3-V or 5-V  
Circuits from Noise Transients  
Port ESD Protection Capability Exceeds:  
− 15-kV Human Body Model  
− 2-kV Machine Model  
Available in a WCSP Chip-Scale Package  
Stand-Off Voltage . . . 6 V Min  
Low Current Leakage . . . 1 µA Max at 6 V  
Low Capacitance . . . 35 pF Typical  
D
USB 1.1 Host, Hub, or Peripheral Ports  
SN65220YZB  
(Size: 925 mm x 925 mm + 6 mm)  
(TOP VIEW)  
SN65220DBV  
(TOP VIEW)  
D
D
D
D
1
2
3
6
5
4
A
NC  
GND  
NC  
A
GND  
B
A1  
B1  
A2  
B2  
GND  
GND  
B
DESCRIPTION  
NC − No internal connection  
When read horizontally, Pin 1 is the bottom left pin.  
The SN65220 is a single transient voltage suppressor and  
the SN65240 and SN75240 are dual transient voltage  
suppressors designed to provide electrical noise transient  
protection to Universal Serial Bus (USB) 1.1 ports. Note  
that the input capacitance of the device makes it  
unsuitable for high-speed USB 2.0 applications.  
SN65240P, SN65240PW  
SN75240P, SN75240PW  
(TOP VIEW)  
1
2
3
4
8
7
6
5
GND  
C
GND  
D
A
GND  
B
Any cabled I/O can be subjected to electrical noise  
transients from various sources. These noise transients  
can cause damage to the USB transceiver and/or the USB  
ASIC if they are of sufficient magnitude and duration.  
GND  
USB ports are typically implemented in 3-V or 5-V digital  
CMOS with very limited ESD protection. The SN65220,  
SN65240, and SN75240 can significantly increase the  
port ESD protection level and reduce the risk of damage  
to the circuits of the USB port.  
CURRENT vs VOLTAGE  
7.5  
The IEC1000-4-2 ESD performance of the SN65220,  
SN65240, and SN75240 is measured at the system level.  
Therefore, system design impacts the results of these  
tests. A high compliance level may be attained with proper  
board design and layout.  
5
2.5  
0
EQUIVALENT SCHEMATIC DIAGRAM  
A or C  
−2.5  
−5  
−7.5  
−10  
GND  
−10  
−5  
0
5
10  
15  
Voltage − V  
B or D  
NOTE A: Typical current versus voltage curve was derived  
using the IEC 1.2/50-µs surge waveform.  
(One Suppressor Shown)  
NOTE All GND terminals should be connected to ground.  
:
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢊꢌ ꢋ ꢔꢈ ꢘ ꢍꢏ ꢋꢁ ꢔ ꢎꢍꢎ ꢙꢚ ꢛꢜ ꢝ ꢞꢟ ꢠꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠꢙ ꢜꢚ ꢨꢟ ꢠꢤꢩ ꢊꢝ ꢜꢨꢣ ꢢꢠꢡ  
ꢢ ꢜꢚ ꢛꢜꢝ ꢞ ꢠꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠꢙ ꢜꢚꢡ ꢥ ꢤꢝ ꢠꢪꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢍꢤꢫ ꢟꢡ ꢏꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚꢨ ꢟꢝ ꢨ ꢬ ꢟꢝ ꢝ ꢟ ꢚꢠꢭꢩ  
ꢊꢝ ꢜ ꢨꢣꢢ ꢠ ꢙꢜ ꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡ ꢡ ꢙꢚ ꢮ ꢨꢜ ꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠꢙ ꢚꢮ ꢜꢛ ꢟꢧ ꢧ ꢥꢟ ꢝ ꢟꢞ ꢤꢠꢤ ꢝ ꢡꢩ  
Copyright 1997 − 2003, Texas Instruments Incorporated  

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