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SN64BCT657 PDF预览

SN64BCT657

更新时间： 2024-11-14 12:22:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
7页 127K
描述
OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS

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SN64BCT657 数据手册

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SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994  
DW OR NT PACKAGE  
(TOP VIEW)  
• State-of-the-Art BiCMOS Design  
Significantly Reduces I  
CCZ  
• ESD Protection Exceeds 2000 V Per  
T/R  
A1  
A2  
A3  
A4  
A5  
OE  
1
24  
MIL-STD-883C, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
23 B1  
22 B2  
3
• High-Impedance State During Power Up  
4
21  
20  
19  
18  
17  
16  
15  
14  
13  
B3  
B4  
GND  
GND  
B5  
B6  
B7  
B8  
PARITY  
and Power Down  
5
6
• 3-State B Outputs Sink 64 mA and Source  
7
V
15 mA  
CC  
A6  
8
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
9
A7  
A8  
10  
11  
12  
ODD/EVEN  
ERR  
description  
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals.  
The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the  
A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode).  
When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.  
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity  
bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity  
generator/checker in the receive mode.  
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic  
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN  
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level  
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.  
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic  
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if  
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR  
is low, indicating a parity error.  
The SN64BCT657 is characterized for operation from −40°C to 85°C and 0°C to 70°C.  
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Copyright 1994, Texas Instruments Incorporated  
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3−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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与SN64BCT657相关器件

型号 品牌 获取价格 描述 数据表
SN64BCT657DW TI

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 		Octal Transceiver With Parity Generator/Checker And 3-State Outputs 24-SOIC -40 to 85
SN64BCT657DWR TI

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 		BCT/FBT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN64BCT657NT TI

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 		Octal Transceiver With Parity Generator/Checker And 3-State Outputs 24-PDIP -40 to 85
SN64BCT757 TI

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 		OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS
SN64BCT757DW TI

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 		OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS
SN64BCT757DWG4 TI

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 		Octal Buffer/Driver With Open-Collector Outputs 20-SOIC -40 to 85
SN64BCT757DWR TI

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 		Octal Buffer/Driver With Open-Collector Outputs 20-SOIC -40 to 85
SN64BCT757DWRG4 TI

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 		BCT/FBT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SO-20
SN64BCT757N TI

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 		OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS
SN64LS138 TI

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 		3-LINE TO 8-LINE DECODERS / DEMUL TIPLEXERS

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