ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢉ ꢅꢆꢊꢋꢌꢍ ꢎꢏ ꢍꢐꢆ ꢑꢒ ꢏꢏ ꢍꢑ ꢍꢎꢌ ꢎꢐꢆ ꢓꢔ ꢍꢌꢕ ꢋ ꢒꢔ ꢐ ꢕꢋꢉ
ꢈ
ꢃ
ꢔ
ꢀ
ꢌ
ꢖ
ꢒ
ꢆ
ꢗ
ꢌ
ꢇ
ꢐ
ꢀ
ꢆ
ꢊ
ꢆ
ꢍ
ꢌ
ꢉ
ꢘ
ꢆ
ꢔ
ꢘ
ꢆ
SCBS066A − JUNE 1990 − REVISED NOVEMBER 1993
DW OR N PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
8Q
8D
7D
7Q
6Q
6D
5D
5Q
• High-Impedance State During Power Up and
Power Down
• 3-State True Outputs Drive Bus Lines or
Buffer-Memory Address Registers
• Full Parallel Access for Loading
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (N)
GND 10
11 CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the SN64BCT374 are edge-triggered D-type flip-flops. On the positive transition of the
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance impedance state and increased drive provide the capability to
drive bus lines without need for interface or pullup components.
The output-enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The outputs are in a high-impedance state during power up and power down when the supply voltage is less
than approximately 3 V.
The SN64BCT374 is characterized for operation from −ā40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
↑
D
H
L
H
L
L
↑
L
L
X
X
Q
0
H
X
Z
ꢔꢑ ꢉ ꢎꢘ ꢅ ꢆꢒ ꢉꢁ ꢎ ꢊꢆꢊ ꢙꢚ ꢛ ꢜꢝ ꢞꢟ ꢠꢙꢜ ꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ
ꢔꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢆꢤꢫ ꢟꢡ ꢒꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢔꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
Copyright 1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443