5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN54LVTH574W
SN54LVTH574W PDF预览

SN54LVTH574W

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 97K
描述
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN54LVTH574W 技术参数

生命周期：Obsolete包装说明：DFP,
Reach Compliance Code：unknown风险等级：5.32
其他特性：BROADSIDE VERSION OF 374系列：LVT
JESD-30 代码：R-GDFP-F20长度：13.09 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：5.5 ns
认证状态：Not Qualified座面最大高度：2.54 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.92 mm
Base Number Matches：1

SN54LVTH574W 数据手册

 浏览型号SN54LVTH574W的Datasheet PDF文件第2页浏览型号SN54LVTH574W的Datasheet PDF文件第3页浏览型号SN54LVTH574W的Datasheet PDF文件第4页浏览型号SN54LVTH574W的Datasheet PDF文件第5页浏览型号SN54LVTH574W的Datasheet PDF文件第6页浏览型号SN54LVTH574W的Datasheet PDF文件第7页 
SN54LVTH574, SN74LVTH574  
3.3-V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS688D – MAY 1997 – REVISED APRIL 1999  
SN54LVTH574 . . . J OR W PACKAGE  
SN74LVTH574 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
13 7Q  
12 8Q  
11 CLK  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
GND 10  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
SN54LVTH574 . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Ceramic (J)  
DIPs  
9 10 11 12 13  
description  
These octal flip-flops are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of  
the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

下载PDF

与SN54LVTH574W相关器件

型号 品牌 获取价格 描述 数据表
SN54LVTH646 TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH646_15 TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH646FK TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH646JT TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH646W TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH652 TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH652_08 TI

获取价格

 		3.3V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH652FK TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH652JT TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN54LVTH652W TI

获取价格

 		3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

与SN54LVTH574W相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证