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SN54LVTH162374WD PDF预览

SN54LVTH162374WD

更新时间： 2024-11-24 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
16页 468K
描述
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54LVTH162374WD 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：CERAMIC, DFP-48针数：48
Reach Compliance Code：unknown风险等级：5.5
Is Samacsys：N系列：LVT
JESD-30 代码：R-GDFP-F48长度：15.748 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
最大电源电流（ICC）：5 mA传播延迟（tpd）：7.4 ns
认证状态：Not Qualified座面最大高度：3.05 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL宽度：9.652 mm
Base Number Matches：1

SN54LVTH162374WD 数据手册

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SN54LVTH162374, SN74LVTH162374  
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS262L–JULY 1993–REVISED OCTOBER 2005  
FEATURES  
SN54LVTH162374. . . WD PACKAGE  
•
Members of the Texas Instruments Widebus™  
Family  
SN74LVTH162374. . . DGG OR DL PACKAGE  
(TOP VIEW)  
•
Output Ports Have Equivalent 22-Ω Series  
Resistors, So No External Resistors Are  
Required  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
2
3
•
•
•
•
•
•
•
•
•
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V VCC  
4
)
5
Support Unregulated Battery Operation Down  
to 2.7 V  
6
7
V
CC  
V
CC  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Flow-Through Architecture Optimizes PCB  
Layout  
V
CC  
V
CC  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
74LVTH162374GRDR  
74LVTH162374ZRDR  
SN74LVTH162374DL  
TOP-SIDE MARKING  
FBGA – GRD  
Tape and reel  
LL2374  
FBGA – ZRD (Pb-free)  
Tube  
Tape and reel  
Tube  
SN74LVTH162374DLR  
74LVTH162374DLG4  
SSOP – DL  
LVTH162374  
LVTH162374  
–40°C to 85°C  
Tape and reel  
74LVTH162374DLRG4  
SN74LVTH162374DGGR  
74LVTH162374DGGRG4  
SN74LVTH162374KR  
74LVTH162374ZQLR  
TSSOP – DGG  
Tape and reel  
VFBGA – GQL  
Tape and reel  
Tube  
LL2374  
VFBGA – ZQL (Pb-free)  
CFP – WD  
–55°C to 125°C  
SNJ54LVTH162374WD  
SNJ54LVTH162374WD  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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