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SN54LVT162245AWD PDF预览

SN54LVT162245AWD

更新时间： 2024-11-04 13:13:43
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SN54LVT162245AWD 数据手册

 浏览型号SN54LVT162245AWD的Datasheet PDF文件第2页浏览型号SN54LVT162245AWD的Datasheet PDF文件第3页浏览型号SN54LVT162245AWD的Datasheet PDF文件第4页浏览型号SN54LVT162245AWD的Datasheet PDF文件第5页浏览型号SN54LVT162245AWD的Datasheet PDF文件第6页浏览型号SN54LVT162245AWD的Datasheet PDF文件第7页 
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SCBS714B − FEBRUARY 2000 − REVISED SEPTEMBER 2003  
SN54LVT162245A . . . WD PACKAGE  
SN74LVT162245A . . . DGG OR DL PACKAGE  
(TOP VIEW)  
D
D
Members of the Texas Instruments  
WidebusFamily  
A-Port Outputs Have Equivalent 22-Ω  
Series Resistors, So No External Resistors  
Are Required  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
D
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
4
3.3-V V  
)
5
CC  
6
D
D
D
D
D
D
D
Support Unregulated Battery Operation  
Down to 2.7 V  
7
V
V
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
9
= 3.3 V, T = 25°C  
A
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
2DIR  
description/ordering information  
The ’LVT162245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage  
(3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment.  
CC  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data  
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses  
are effectively isolated.  
ORDERING INFORMATION  
ORDERABLE  
†
T
PACKAGE  
TOP-SIDE MARKING  
A
PART NUMBER  
SN74LVT162245ADL  
SN74LVT162245ADLR  
SN74LVT162245ADGGR  
SN74LVT162245AGQLR  
SN74LVT162245AZQLR  
SNJ54LVT162245AWD  
Tube  
SSOP − DL  
LVT162245A  
LVT162245A  
Tape and reel  
Tape and reel  
TSSOP − DGG  
VFBGA − GQL  
VFBGA − ZQL (Pb-free)  
CFP − WD  
−40°C to 85°C  
−55°C to 125°C  
Tape and reel  
Tube  
LZ245A  
SNJ54LVT162245AWD  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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