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SN54LVC00AJ PDF预览

SN54LVC00AJ

更新时间: 2024-11-22 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路输入元件
页数 文件大小 规格书
8页 113K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54LVC00AJ 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58系列:LVC/LCX/Z
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE传播延迟(tpd):5.1 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN54LVC00AJ 数据手册

 浏览型号SN54LVC00AJ的Datasheet PDF文件第2页浏览型号SN54LVC00AJ的Datasheet PDF文件第3页浏览型号SN54LVC00AJ的Datasheet PDF文件第4页浏览型号SN54LVC00AJ的Datasheet PDF文件第5页浏览型号SN54LVC00AJ的Datasheet PDF文件第6页浏览型号SN54LVC00AJ的Datasheet PDF文件第7页 
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCAS279G – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC00A . . . J OR W PACKAGE  
SN74LVC00A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
2Y  
GND  
= 3.3 V, T = 25°C  
CC  
A
8
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
SN54LVC00A . . . FK PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and DIPs (J)  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
description  
NC  
2B  
15 NC  
14  
9 10 11 12 13  
3B  
The SN54LVC00A quadruple 2-input positive-  
NAND gate is designed for 2.7-V to 3.6-V V  
CC  
operation and the SN74LVC00A quadruple  
2-inputpositive-NANDgateisdesignedfor1.65-V  
to 3.6-V V  
operation.  
CC  
NC – No internal connection  
The ’LVC00A devices perform the Boolean  
function Y = A B or Y = A + B in positive logic.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC00A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVC00A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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