SN54LV74A

更新时间： 2024-11-25 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	159K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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SN54LV74A 数据手册

SN54LV74A, SN74LV74A

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

SCLS381D – AUGUST 1997 – REVISED JUNE 1998

SN54LV74A . . . J OR W PACKAGE

SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Process

Typical V (Output Ground Bounce)

OLP

< 0.8 V at V , T = 25°C

1CLR

2CLR

Typical V

> 2 V at V , T = 25°C

(Output V

Undershoot)

OHV

1CLK

1PRE

2CLK

Latch-Up Performance Exceeds 250 mA Per

JESD 17

10 2PRE

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

GND

SN54LV74A . . . FK PACKAGE

(TOP VIEW)

Package Options Include Plastic

Small-Outline (D, NS), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), and

Thin Shrink Small-Outline (PW) Packages,

Ceramic Flat (W) Packages, Chip Carriers

(FK), and DIPs (J)

20 19

1CLK

description

2CLK

1PRE

15 NC

These dual positive-edge-triggered D-type

flip-flops are designed for 2-V to 5.5-V V

operation.

2PRE

9 10 11 12 13

A low level at the preset (PRE) or clear (CLR)

inputs sets or resets the outputs, regardless of the

levels of the other inputs. When PRE and CLR are

inactive (high), data at the data (D) inputs meeting

the setup-time requirements is transferred to the

outputs on the positive-going edge of the clock

pulse. Clock triggering occurs at a voltage level

and is not directly related to the rise time of the

clock pulse. Following the hold-time interval, data

attheDinputcanbechangedwithoutaffectingthe

levels at the outputs.

NC – No internal connection

The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LV74A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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与SN54LV74A相关器件

型号	品牌	获取价格	描述	数据表
SN54LV74AFK	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV74AJ	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV74AW	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV74AWR	TI	获取价格	暂无描述
SN54LV74FK	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV74J	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV74W	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN54LV86A	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LV86A_07	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54LV86A_08	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

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