Datasheet > 逻辑 > 栅极> SN54LV32

SN54LV32

更新时间： 2024-11-25 12:47:03

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
10页	221K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATES

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN54LV32 数据手册

ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ

ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢋꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢔ ꢎ ꢕ ꢌꢓꢐ ꢀ

SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996

SN54LV32 . . . J OR W PACKAGE

SN74LV32 . . . D, DB, OR PW PACKAGE

(TOP VIEW)

EPIC  (Enhanced-Performance Implanted

CMOS) 2-µ Process

Typical V

(Output Ground Bounce)

OLP

< 0.8 V at V , T = 25°C

Typical V

(Output V

Undershoot)

OHV

> 2 V at V , T = 25°C

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

10 3B

GND

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

SN54LV32 . . . FK PACKAGE

(TOP VIEW)

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

20 19

description

15 NC

9 10 11 12 13

These quadruple 2-input positive-OR gates are

designed for 2.7-V to 5.5-V V operation.

The ’LV32 perform the Boolean function

Y = A + B or Y =

in positive logic.

NC − No internal connection

The SN74LV32 is packaged in TI’s shrink

small-outline package (DB), which provides the

same I/O pin count and functionality of standard

small-outline packages in less than half the

printed-circuit-board area.

The SN54LV32 is characterized for operation over the full military temperature range of −55°C to 125°C. The

SN74LV32 is characterized for operation from −40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

ꢋ ꢁ ꢄꢐꢀꢀ ꢔ ꢓꢖ ꢐꢎꢗ ꢒꢀ ꢐ ꢁ ꢔꢓꢐꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢎ ꢔ ꢍ ꢋ ꢤꢓ ꢒꢔ ꢁ

ꢪ

ꢍ

ꢌ

ꢓ

ꢌ

ꢚ

ꢢ

ꢥ

ꢝ

ꢦ

ꢠ

ꢣ

ꢘ

ꢚ

ꢝ

ꢢ

ꢞ

ꢟ

ꢦ

ꢡ

ꢢ

ꢘ

ꢣ

ꢛ

ꢝ

ꢥ

ꢧ

ꢟ

ꢨ

ꢩ

ꢚ

ꢞ

ꢣ

ꢘ

ꢚ

ꢝ

ꢢ

ꢜ

ꢣ

ꢘ

ꢡ

ꢏ

ꢦ

ꢝ

ꢜ

ꢟ

ꢞ

ꢘ

ꢛ

ꢞ

ꢝ

ꢢ

ꢥ

ꢝ

ꢦ

ꢠ

ꢘ

ꢝ

ꢛ

ꢧ

ꢡ

ꢞ

ꢚ

ꢥ

ꢚ

ꢞ

ꢣ

ꢘ

ꢚ

ꢝ

ꢢ

ꢛ

ꢧ

ꢡ

ꢦ

ꢘ

ꢙ

ꢡ

ꢘ

ꢡ

ꢦ

ꢠ

ꢛ

ꢝ

ꢥ

ꢓ

ꢡ

ꢫ

ꢣ

ꢛ

ꢒ

ꢢ

ꢛ

ꢘ

ꢦ

ꢟ

ꢠ

ꢡ

ꢢ

ꢘ

ꢛ

ꢘ

ꢣ

ꢢ

ꢜ

ꢣ

ꢦ

ꢜ

ꢬ

ꢣ

ꢦ

ꢣ

ꢢ

ꢘ

ꢭ

ꢪ

ꢏ

ꢦ

ꢝ

ꢜ

ꢟ

ꢞ

ꢘ

ꢚ

ꢧꢣ ꢦ ꢣ ꢠ ꢡ ꢘ ꢡ ꢦ ꢛ ꢪ

ꢝ

ꢢ

ꢧ

ꢦ

ꢝ

ꢞ

ꢡ

ꢛ

ꢚ

ꢢ

ꢮ

ꢜ

ꢝ

ꢡ

ꢛ

ꢢ

ꢝ

ꢘ

ꢢ

ꢡ

ꢞ

ꢡ

ꢛ

ꢣ

ꢦ

ꢚ

ꢩ

ꢭ

ꢚ

ꢢ

ꢞ

ꢩ

ꢟ

ꢜ

ꢡ

ꢘ

ꢡ

ꢛ

ꢘ

ꢚ

ꢢ

ꢮ

ꢝ

ꢥ

ꢣ

ꢩ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...10

中文翻译

下载PDF

与SN54LV32相关器件

型号	品牌	获取价格	描述	数据表
SN54LV32A	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54LV32A_06	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54LV32AFK	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54LV32AJ	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54LV32AW	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54LV32FK	TI	获取价格	暂无描述
SN54LV32J	TI	获取价格	暂无描述
SN54LV367A	TI	获取价格	HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SN54LV367AFK	TI	获取价格	HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SN54LV367AJ	TI	获取价格	HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

与SN54LV32相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

42
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

33
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

61
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

57

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54LV32

SN54LV32 数据手册

与SN54LV32相关器件

与SN54LV32相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54LV32

SN54LV32 数据手册

与SN54LV32相关器件

与SN54LV32相关文章

您还可以找

您在本页遇到什么问题？