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ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢋꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢔ ꢎ ꢕ ꢌꢓꢐ ꢀ
SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996
SN54LV32 . . . J OR W PACKAGE
SN74LV32 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at V , T = 25°C
CC
A
1A
1B
V
CC
1
2
3
4
5
6
7
14
13
12
11
Typical V
(Output V
Undershoot)
4B
4A
4Y
OHV
OH
> 2 V at V , T = 25°C
1Y
CC
A
2A
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
2B
10 3B
9
8
2Y
3A
3Y
GND
D
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
SN54LV32 . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
2A
4
5
6
7
8
17
16
description
15 NC
14
9 10 11 12 13
NC
2B
These quadruple 2-input positive-OR gates are
designed for 2.7-V to 5.5-V V operation.
3B
CC
The ’LV32 perform the Boolean function
Y = A + B or Y =
in positive logic.
B
A
@
NC − No internal connection
The SN74LV32 is packaged in TI’s shrink
small-outline package (DB), which provides the
same I/O pin count and functionality of standard
small-outline packages in less than half the
printed-circuit-board area.
The SN54LV32 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV32 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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