Datasheet > SN54LV165FK

SN54LV165FK

更新时间： 2024-11-26 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		移位寄存器
页数	文件大小	规格书
8页	168K
描述
PARALLEL-LOAD 8-BIT SHIFT REGISTERS

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SN54LV165FK 数据手册

SN54LV165, SN74LV165

PARALLEL-LOAD 8-BIT SHIFT REGISTERS

SCES007B – MARCH 1995 – REVISED APRIL 1996

EPIC (Enhanced-Performance Implanted

CMOS) 2-µ Process

SN54LV165 . . . J OR W PACKAGE

SN74LV165 . . . D, DB, OR PW PACKAGE

(TOP VIEW)

Typical V

< 0.8 V at V , T = 25°C

(Output Ground Bounce)

OLP

SH/LD

Typical V

< 2 V at V , T = 25°C

(Output V

Undershoot)

OHV

CLK

CLK INH

ESDProtectionExceeds2000VPer

MIL-STD-883C,Method3015;Exceeds200V

UsingMachineModel(C=200pF, R=0)

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

SER

GND

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

SN54LV165 . . . FK PACKAGE

(TOP VIEW)

description

20 19

The ’LV165 parallel-load, 8-bit shift registers are

designed for 2.7-V to 5.5-V V operation.

When the device is clocked, data is shifted toward

the serial output Q . Parallel-in access to each

stage is provided by eight individual direct data

inputs that are enabled by a low level at the SH/LD

input. The ’LV165 feature a clock inhibit function

9 10 11 12 13

and a complemented serial output Q .

Clocking is accomplished by a low-to-high

transition of the clock (CLK) input while SH/LD is

NC – No internal connection

held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are

interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK

INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held

high. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,

CLK INH, or SER.

The SN54LV165 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LV165 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OPERATION

SH/LD

CLK

CLK INH

↑

Parallel load

Shift

↑

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7 8

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与SN54LV165FK相关器件

型号	品牌	获取价格	描述	数据表
SN54LV165J	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54LV165W	TI	获取价格	PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SN54LV166A	TI	获取价格	8-BIT PARALLEL-LOAD SHIFT REGISTERS
SN54LV166A_08	TI	获取价格	8-BIT PARALLEL-LOAD SHIFT REGISTERS
SN54LV174	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN54LV174A	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN54LV174AFK	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN54LV174AJ	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN54LV174AW	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR
SN54LV174FK	TI	获取价格	HEX D-TYPE FLIP-FLOPS WITH CLEAR

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