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SN54LV00AFK PDF预览

SN54LV00AFK

更新时间: 2024-11-01 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
7页 132K
描述
LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NAND GATE, CQCC20, CERAMIC, LCC-20

SN54LV00AFK 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:LV/LV-A/LVX/H
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):21 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SN54LV00AFK 数据手册

 浏览型号SN54LV00AFK的Datasheet PDF文件第2页浏览型号SN54LV00AFK的Datasheet PDF文件第3页浏览型号SN54LV00AFK的Datasheet PDF文件第4页浏览型号SN54LV00AFK的Datasheet PDF文件第5页浏览型号SN54LV00AFK的Datasheet PDF文件第6页浏览型号SN54LV00AFK的Datasheet PDF文件第7页 
SN54LV00, SN74LV00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCLS182C – FEBRUARY 1993 – REVISED APRIL 1996  
SN54LV00 . . . J OR W PACKAGE  
SN74LV00 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
4B  
4A  
4Y  
3B  
3A  
3Y  
A
1Y  
2A  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2B  
2Y  
GND  
8
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV00 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
description  
17  
16  
15  
14  
These quadruple 2-input positive-NAND gates  
are designed for 2.7-V to 5.5-V V operation.  
NC  
2B  
CC  
9 10 11 12 13  
The ’LV00 perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
The SN74LV00 is available in TI’s shrink  
small-outline package (DB), which provides the  
same I/O pin count and functionality of standard  
small-outline packages in less than half the  
printed-circuit-board area.  
NC – No internal connection  
The SN54LV00 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV00 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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