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SN54LS642J PDF预览

SN54LS642J

更新时间: 2024-11-11 23:03:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
3页 122K
描述
OCTAL BUS TRANSCEIVERS

SN54LS642J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
风险等级:5.92Is Samacsys:N
其他特性:WITH COMMON OUTPUT ENABLE AND DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-CDIP-T20JESD-609代码:e0
长度:24.515 mm负载电容(CL):45 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.012 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-COLLECTOR输出极性:INVERTED
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):90 mA
Prop。Delay @ Nom-Sup:25 ns传播延迟(tpd):25 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN54LS642J 数据手册

 浏览型号SN54LS642J的Datasheet PDF文件第2页浏览型号SN54LS642J的Datasheet PDF文件第3页 
SN54/74LS640  
SN54/74LS641  
SN54/74LS642  
SN54/74LS645  
OCTAL BUS TRANSCEIVERS  
These octal bus transceivers are designed for asynchronous two-way  
communication between data buses. Control function implementation  
minimizes external timing requirements. These circuits allow data transmis-  
sion from the A bus to B or from the B bus to A bus depending upon the logic  
level of the direction control (DIR) input. Enable input (G) can disable the  
device so that the buses are effectively isolated.  
OCTAL BUS TRANSCEIVERS  
LOW POWER SCHOTTKY  
DEVICE  
LS640  
LS641  
LS642  
LS645  
OUTPUT  
3-State  
Open-Collector  
Open-Collector  
3-State  
LOGIC  
Inverting  
True  
Inverting  
True  
J SUFFIX  
CERAMIC  
CASE 732-03  
FUNCTION TABLE  
20  
CONTROL  
INPUTS  
OPERATION  
1
LS640  
LS642  
LS641  
LS645  
G
L
DIR  
L
N SUFFIX  
PLASTIC  
CASE 738-03  
B data to A bus  
A data to B bus  
Isolation  
B data to A bus  
A data to B bus  
Isolation  
20  
L
H
1
H
X
H = HIGH Level, L = LOW Level, X = Irrelevant  
DW SUFFIX  
SOIC  
CASE 751D-03  
20  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXDW SOIC  
CONNECTION DIAGRAMS DIP (TOP VIEW)  
ENABLE  
ENABLE  
V
B1  
18  
B2  
17  
B3  
16  
B4  
15  
B5  
14  
B6 B7  
B8  
11  
V
B1  
18  
B2  
17  
B3  
16  
B4  
15  
B5  
14  
B6 B7  
B8  
11  
G
G
CC  
20  
CC  
20  
19  
13  
12  
19  
13  
12  
1
2
3
4
5
6
8
9
10  
1
2
3
4
5
6
8
9
10  
7
7
DIR A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
DIR A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8 GND  
SN54/74LS640  
SN54/74LS642  
SN54/74LS641  
SN54/74LS645  
FAST AND LS TTL DATA  
5-1  

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