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SN54LS273J PDF预览

SN54LS273J

更新时间: 2024-09-15 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路触发器锁存器
页数 文件大小 规格书
8页 424K
描述
具有清零端的八路 D 型触发器 | J | 20 | -55 to 125

SN54LS273J 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-20针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.02Is Samacsys:N
系列:LSJESD-30 代码:R-GDIP-T20
长度:24.2 mm负载电容(CL):15 pF
逻辑集成电路类型:D FLIP-FLOP最大I(ol):0.008 A
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):27 mA传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mm最小 fmax:30 MHz
Base Number Matches:1

SN54LS273J 数据手册

 浏览型号SN54LS273J的Datasheet PDF文件第2页浏览型号SN54LS273J的Datasheet PDF文件第3页浏览型号SN54LS273J的Datasheet PDF文件第4页浏览型号SN54LS273J的Datasheet PDF文件第5页浏览型号SN54LS273J的Datasheet PDF文件第6页浏览型号SN54LS273J的Datasheet PDF文件第7页 
SN54273, SN54LS273, SN74273, SN74LS273  
OCTAL D-TYPE FLIP-FLOP WITH CLEAR  
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988  
SN54273, SN74LS273 . . . J OR W PACKAGE  
SN74273 . . . N PACKAGE  
Contains Eight Flip-Flops With Single-Rail  
Outputs  
SN74LS273 . . . DW OR N PACKAGE  
(TOP VIEW)  
Buffered Clock and Direct Clear Inputs  
Individual Data Input to Each Flip-Flop  
Applications Include:  
Buffer/Storage Registers  
Shift Registers  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
8Q  
8D  
7D  
Pattern Generators  
16 7Q  
15 6Q  
description  
14  
13  
12  
11  
6D  
5D  
5Q  
CLK  
These monolithic, positive-edge-triggered flip-  
flops utilize TTL circuitry to implement D-type  
flip-flop logic with a direct clear input.  
GND  
Information at the D inputs meeting the setup time  
requirements is transferred to the Q outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a particular voltage level and  
is not directly related to the transition time of the  
positive-going pulse. When the clock input is at  
either the high or low level, the D input signal has  
no effect ar the output.  
SN54LS273 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
These flip-flops are guaranteed to respond to  
clock frequencies ranging form 0 to 30 megahertz  
while maximum clock frequency is typically 40  
megahertz. Typical power dissipation is 39  
milliwatts per flip-flop for the 273 and 10 milliwatts  
for the LS273.  
17  
16  
15  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each flip-flop)  
logic symbol  
INPUTS  
1
CLR  
OUTPUT  
Q
EN  
C1  
CLEAR CLOCK  
D
X
H
L
11  
CLK  
L
H
H
H
X
L
H
L
3
1D  
4
2
5
6
1D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
2D  
7
L
X
Q
0
3D  
8
9
4D  
13  
5D  
14  
6D  
17  
7D  
18  
8D  
12  
15  
16  
19  
This symbol is in accordance with ANSI/IEEE Std.  
91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the DW, J, N, and W packages.  
Copyright 1988, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN54LS273J 替代型号

型号 品牌 替代类型 描述 数据表
JM38510/32501BRA TI

完全替代

具有清零端的八路 D 型触发器 | J | 20 | -55 to 125
SNJ54ABT273W TI

完全替代

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR
SNJ54ABT273J TI

完全替代

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR

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