SN54LS273

更新时间： 2024-09-07 23:03:03

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
5页	187K
描述
OCTAL D FLIP-FLOP WITH CLEAR

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数据手册

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SN54LS273 数据手册

SN54/74LS273

OCTAL D FLIP-FLOP WITH CLEAR

The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of

eight D-Type Flip-Flops with a Common Clock and an asynchronous active

LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3

inch lead spacing.

• 8-Bit High Speed Register

• Parallel Register

OCTAL D FLIP-FLOP

WITH CLEAR

• Common Clock and Master Reset

• Input Clamp Diodes Limit High-Speed Termination Effects

LOW POWER SCHOTTKY

CONNECTION DIAGRAM DIP (TOP VIEW)

J SUFFIX

CERAMIC

CASE 732-03

N SUFFIX

PLASTIC

CASE 738-03

PIN NAMES

LOADING (Note a)

HIGH

LOW

Clock (Active HIGH Going Edge) Input

Data Inputs

Master Reset (Active LOW) Input

0.5 U.L.

10 U.L.

0.25 U.L.

DW SUFFIX

SOIC

CASE 751D-03

D –D

Q –Q

5 (2.5) U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) Temperature Ranges.

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

TRUTH TABLE

SN74LSXXXN Plastic

SN74LSXXXDW SOIC

MR CP

H = HIGH Logic Level

L = LOW Logic Level

X = Immaterial

LOGIC DIAGRAM

FAST AND LS TTL DATA

5-447

12 3 4 5

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与SN54LS273相关器件

型号	品牌	获取价格	描述	数据表
SN54LS273FK	TI	获取价格	OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SN54LS273J	MOTOROLA	获取价格	OCTAL D FLIP-FLOP WITH CLEAR
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SN54LS275	TI	获取价格	4 BIT BY 4 BIT BINARY MULTIPLER WITH 3-STATE OUTPUTS
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