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SN54LS196 PDF预览

SN54LS196

更新时间: 2024-11-22 23:06:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
8页 229K
描述
4-STAGE PRESETTABLE RIPPLE COUNTERS

SN54LS196 数据手册

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SN54/74LS196  
SN54/74LS197  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddi-  
vide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1)  
sequence or in a bi-quinary mode producing a 50% duty cycle output. The  
SN54/74LS197 contains divide-by-two and divide-by-eight sections which  
can be combined to form a modulo-16 binary counter. Low Power Schottky  
technology is used to achieve typical count rates of 70 MHz and power dis-  
sipation of only 80 mW.  
4-STAGE PRESETTABLE  
RIPPLE COUNTERS  
LOW POWER SCHOTTKY  
Both circuit types have a Master Reset (MR) input which overrides all other  
inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL)  
overrides clocked operations and asynchronously loads the data on the Par-  
allel Data inputs (P ) into the flip-flops. This preset feature makes the circuits  
n
J SUFFIX  
CERAMIC  
CASE 632-08  
usable as programmable counters. The circuits can also be used as 4-bit  
latches, loading data from the Parallel Data inputs when PL is LOW and stor-  
ing the data when PL is HIGH.  
14  
1
Low Power Consumption — Typically 80 mW  
High Counting Rates — Typically 70 MHz  
Choice of Counting Modes — BCD, Bi-Quinary, Binary  
Asynchronous Presettable  
Asynchronous Master Reset  
Easy Multistage Cascading  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
Input Clamp Diodes Limit High Speed Termination Effects  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
1.5 U.L.  
CP  
Clock (Active LOW Going Edge)  
Input to Divide-by-Two Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Five Section  
Clock (Active LOW Going Edge)  
Input to Divide-by-Eight Section  
Master Reset (Active LOW) Input  
Parallel Load (Active LOW) Input  
Data Inputs  
1.0 U.L.  
0
CP (LS196)  
2.0 U.L.  
1.0 U.L.  
1.75 U.L.  
0.8 U.L.  
1
CP (LS197)  
1
MR  
PL  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
P –P  
0
0.25 U.L.  
3
Q –Q  
Outputs (Notes b, c)  
5 (2.5) U.L.  
0
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
c. In addition to loading shown, Q can also drive CP .  
0
1
FAST AND LS TTL DATA  
5-372  

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