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SN54LS132J PDF预览

SN54LS132J

更新时间: 2024-11-25 23:06:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
5页 160K
描述
QUAD 2-INPUT SCHMITT TRIGGER NAND GATE

SN54LS132J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.27
Is Samacsys:N系列:LS
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.495 mm负载电容(CL):15 pF
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED最大电源电流(ICC):14 mA
传播延迟(tpd):22 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN54LS132J 数据手册

 浏览型号SN54LS132J的Datasheet PDF文件第2页浏览型号SN54LS132J的Datasheet PDF文件第3页浏览型号SN54LS132J的Datasheet PDF文件第4页浏览型号SN54LS132J的Datasheet PDF文件第5页 
SN54/74LS132  
QUAD 2-INPUT  
SCHMITT TRIGGER NAND GATE  
The SN54/74LS132 contains four 2-Input NAND Gates which accept stan-  
dard TTL input signals and provide standard TTL output levels. They are ca-  
pableof transforming slowly changing input signals into sharply defined, jitter-  
free output signals. Additionally, they have greater noise margin than  
conventional NAND Gates.  
Each circuit contains a 2-input Schmitt trigger followed by a Darlington level  
shifterandaphasesplitterdrivingaTTLtotempoleoutput. TheSchmitttrigger  
uses positive feedback to effectively speed-up slow input transitions, and  
provide differentinput threshold voltages for positive and negative-going tran-  
sitions. This hysteresis between the positive-going and negative-going input  
thresholds (typically 800 mV) is determined internally by resistor ratios and is  
essentially insensitive to temperature and supply voltage variations. As long  
QUAD 2-INPUT  
SCHMITT TRIGGER NAND GATE  
LOW POWER SCHOTTKY  
J SUFFIX  
CERAMIC  
CASE 632-08  
as one input remains at a more positive voltage than V (MAX), the gate will  
T+  
respond to the transitions of the other input as shown in Figure 1.  
14  
1
LOGIC AND CONNECTION DIAGRAM  
DIP (TOP VIEW)  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
1
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
ORDERING INFORMATION  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
°
Figure 1. V versus V  
IN OUT  
Transfer Function  
FAST AND LS TTL DATA  
5-212  

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