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SN54HCT00 PDF预览

SN54HCT00

更新时间: 2024-11-25 23:03:03
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描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HCT00 数据手册

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SN54HCT00, SN74HCT00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCLS062B – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT00 . . . J OR W PACKAGE  
SN74HCT00 . . . D, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
2A  
2B  
10 3B  
description  
9
8
2Y  
3A  
3Y  
These devices contain four independent 2-input  
NAND gates. They perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
GND  
SN54HCT00 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT00 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT00 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each gate)  
INPUTS  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
OUTPUT  
Y
3B  
A
H
L
B
H
X
L
L
H
H
X
NC – No internal connection  
logic symbol  
1
1A  
&
3
2
1Y  
1B  
2A  
2B  
3A  
3B  
4A  
4B  
4
6
5
2Y  
9
8
10  
12  
13  
3Y  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, PW, and W packages.  
logic diagram (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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