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SN54HC684FK PDF预览

SN54HC684FK

更新时间: 2024-11-25 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 运算电路逻辑集成电路输出元件
页数 文件大小 规格书
7页 121K
描述
8-BIT MAGNITUDE COMPARATORS

SN54HC684FK 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:CERAMIC, LCC-20针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
其他特性:WITH A=B AND A > B OUTPUTS系列:HC/UH
JESD-30 代码:S-CQCC-N20长度:8.89 mm
逻辑集成电路类型:MAGNITUDE COMPARATOR位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):413 ns认证状态:Not Qualified
座面最大高度:2.03 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

SN54HC684FK 数据手册

 浏览型号SN54HC684FK的Datasheet PDF文件第2页浏览型号SN54HC684FK的Datasheet PDF文件第3页浏览型号SN54HC684FK的Datasheet PDF文件第4页浏览型号SN54HC684FK的Datasheet PDF文件第5页浏览型号SN54HC684FK的Datasheet PDF文件第6页浏览型号SN54HC684FK的Datasheet PDF文件第7页 
SN54HC684, SN74HC684  
8-BIT MAGNITUDE COMPARATORS  
SCLS340A – MARCH 1996 – REVISED MAY 1997  
SN54HC684 . . . J OR W PACKAGE  
SN74HC684 . . . DW OR N PACKAGE  
(TOP VIEW)  
Compare Two 8-Bit Words  
Package Options Include Plastic  
Small-Outline (DW) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
P > Q  
P0  
V
CC  
P = Q  
Q7  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Q0  
P1  
17 P7  
16 Q6  
15 P6  
14 Q5  
13 P5  
12 Q4  
11 P4  
description  
Q1  
P2  
These  
magnitude  
comparators  
perform  
Q2  
P3  
comparisons of two 8-bit binary or BCD words.  
These devices provide P = Q and P > Q outputs.  
Q3  
The SN54HC684 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC684 is characterized for  
operation from –40°C to 85°C.  
GND 10  
SN54HC684 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
DATA  
INPUTS  
P, Q  
OUTPUTS  
P = Q P > Q  
3
2
1
20 19  
18  
Q7  
P7  
Q6  
P1  
Q1  
P2  
Q2  
P3  
4
5
6
7
8
P = Q  
P > Q  
P < Q  
L
H
H
H
L
17  
16  
H
15 P6  
14  
9 10 11 12 13  
The P < Q function can be  
generated by applying P = Q  
and P > Q to a 2-input NAND  
gate.  
Q5  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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