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SN54HC374FKR PDF预览

SN54HC374FKR

更新时间: 2024-11-02 13:13:43
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 109K
描述
HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

SN54HC374FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.4Is Samacsys:N
系列:HC/UHJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):345 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SN54HC374FKR 数据手册

 浏览型号SN54HC374FKR的Datasheet PDF文件第2页浏览型号SN54HC374FKR的Datasheet PDF文件第3页浏览型号SN54HC374FKR的Datasheet PDF文件第4页浏览型号SN54HC374FKR的Datasheet PDF文件第5页浏览型号SN54HC374FKR的Datasheet PDF文件第6页浏览型号SN54HC374FKR的Datasheet PDF文件第7页 
SN54HC374, SN74HC374  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCLS141C – DECEMBER 1982 – REVISED JULY 1998  
SN54HC374 . . . J OR W PACKAGE  
SN74HC374 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
Eight D-Type Flip-Flops in a Single Package  
High-Current 3-State True Outputs Can  
Drive up to 15 LSTTL Loads  
Full Parallel Access for Loading  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Package Options Include Plastic Shrink  
Small-Outline (DB), Small-Outline (DW),  
Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) DIPs  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
description  
GND 10  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
SN54HC374 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
The eight flip-flops of the ’HC374 devices are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock (CLK) input, the Q outputs  
are set to the logic levels that were set up at the  
data (D) inputs.  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15 6Q  
14  
9 10 11 12 13  
6D  
An output-enable (OE) input places the eight  
outputs in either a normal logic state (high or low  
logic levels) or the high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive  
bus lines without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54HC374 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74HC374 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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