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SN54HC368J PDF预览

SN54HC368J

更新时间: 2024-11-22 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
15页 462K
描述
HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HC368J 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-16针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.1Is Samacsys:N
其他特性:ONE FUNCTION WITH TWO BITS控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A位数:4
功能数量:2端口数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.16 mA
Prop。Delay @ Nom-Sup:29 ns传播延迟(tpd):180 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.92 mm
Base Number Matches:1

SN54HC368J 数据手册

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SCLS310D − JANUARY 1996 −REVISED OCTOBER 2003  
SN54HC368 . . . J OR W PACKAGE  
SN74HC368 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Drive Bus  
Lines, Buffer Memory Address Registers,  
or Drive Up To 15 LSTTL Loads  
1OE  
1A1  
1Y1  
1A2  
1Y2  
1A3  
1Y3  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
2OE  
2A2  
2Y2  
D
D
D
D
D
Inverting Outputs  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 10 ns  
pd  
6-mA Output Drive at 5 V  
12 2A1  
11  
10  
9
2Y1  
1A4  
1Y4  
Low Input Current of 1 µA Max  
description/ordering information  
SN54HC368 . . . FK PACKAGE  
(TOP VIEW)  
These hex inverting buffers and line drivers are  
designed specifically to improve both the  
performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented  
receivers and transmitters. The ’HC368 devices  
are organized as dual 4-line and 2-line  
buffers/drivers with active-low output-enable  
(1OE and 2OE) inputs. When OE is low, the  
device passes inverted data from the A inputs to  
the Y outputs. When OE is high, the outputs are  
in the high-impedance state.  
3
2
1
20 19  
18  
2A2  
2Y2  
NC  
1Y1  
1A2  
NC  
4
5
6
7
8
17  
16  
15 2A1  
14  
9 10 11 12 13  
1Y2  
1A3  
2Y1  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC368N  
SN74HC368N  
SN74HC368D  
SN74HC368DR  
SN74HC368DT  
SN74HC368NSR  
SN74HC368DBR  
SN74HC368PW  
SN74HC368PWR  
SN74HC368PWT  
SNJ54HC368J  
HC368  
SOP − NS  
HC368  
HC368  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC368  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC368J  
SNJ54HC368W  
SNJ54HC368FK  
−55°C to 125°C  
SNJ54HC368W  
SNJ54HC368FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢚ ꢝ ꢨ ꢠ ꢟꢫ ꢦꢥ ꢣꢤ ꢥꢟ ꢡꢨ ꢪꢜ ꢢꢝ ꢣ ꢣꢟ ꢲꢍ ꢗꢙ ꢛꢏ ꢔ ꢙꢆꢈꢂ ꢆꢂꢉ ꢢꢪꢪ ꢨꢢ ꢠ ꢢ ꢡꢧ ꢣꢧꢠ ꢤ ꢢ ꢠ ꢧ ꢣꢧ ꢤꢣꢧ ꢫ  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢦ ꢝꢪ ꢧꢤꢤ ꢟ ꢣꢭꢧ ꢠ ꢯꢜ ꢤꢧ ꢝ ꢟꢣꢧ ꢫꢬ ꢚ ꢝ ꢢꢪ ꢪ ꢟ ꢣꢭꢧ ꢠ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢤ ꢉ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟ ꢝ  
ꢝꢥ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN54HC368J 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC368E TI

完全替代

High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting
SNJ54HC368J TI

完全替代

HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
CD54HC368F3A TI

完全替代

High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting

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