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SN54HC174J PDF预览

SN54HC174J

更新时间: 2024-11-25 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 95K
描述
HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC174J 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.12
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.0052 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
最大电源电流(ICC):0.08 mAProp。Delay @ Nom-Sup:48 ns
传播延迟(tpd):240 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.92 mm
最小 fmax:25 MHzBase Number Matches:1

SN54HC174J 数据手册

 浏览型号SN54HC174J的Datasheet PDF文件第2页浏览型号SN54HC174J的Datasheet PDF文件第3页浏览型号SN54HC174J的Datasheet PDF文件第4页浏览型号SN54HC174J的Datasheet PDF文件第5页浏览型号SN54HC174J的Datasheet PDF文件第6页 
SN54HC174, SN74HC174  
HEX D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS119B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC174 . . . J OR W PACKAGE  
SN74HC174 . . . D OR N PACKAGE  
(TOP VIEW)  
Contain Six Flip-Flops With Single-Rail  
Outputs  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
6Q  
6D  
5D  
5Q  
4D  
4Q  
CLK  
– Pattern Generators  
1D  
2D  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
2Q  
3D  
3Q  
GND  
description  
SN54HC174 . . . FK PACKAGE  
(TOP VIEW)  
These monolithic positive-edge-triggered D-type  
flip-flops have a direct clear (CLR) input.  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going edge of  
CLK. When CLK is at either the high or low level,  
the D input has no effect at the output.  
3
2
1
20 19  
18 6D  
1D  
2D  
NC  
2Q  
3D  
4
5
6
7
8
17  
16  
15  
14  
5D  
NC  
5Q  
4D  
9 10 11 12 13  
The SN54HC174 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC174 is characterized for  
operation from –40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
L
H
L
H
H
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN54HC174J 替代型号

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