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SN54HC166W PDF预览

SN54HC166W

更新时间： 2024-02-24 01:33:53
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
9页 136K
描述
8-BIT PARALLEL-LOAD SHIFT REGISTERS

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SN54HC166W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.69其他特性：CLOCK INHIBIT
计数方向：RIGHT系列：HC/UH
JESD-30 代码：R-GDFP-F16长度：10.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：PARALLEL IN SERIAL OUT
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：225 ns认证状态：Not Qualified
座面最大高度：2.03 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：6.73 mm
最小 fmax：25 MHzBase Number Matches：1

SN54HC166W 数据手册

 浏览型号SN54HC166W的Datasheet PDF文件第2页浏览型号SN54HC166W的Datasheet PDF文件第3页浏览型号SN54HC166W的Datasheet PDF文件第4页浏览型号SN54HC166W的Datasheet PDF文件第5页浏览型号SN54HC166W的Datasheet PDF文件第6页浏览型号SN54HC166W的Datasheet PDF文件第7页 
SN54HC166, SN74HC166  
8-BIT PARALLEL-LOAD SHIFT REGISTERS  
SCLS117B – DECEMBER 1982 – REVISED MAY 1997  
SN54HC166 . . . J OR W PACKAGE  
SN74HC166 . . . D OR N PACKAGE  
(TOP VIEW)  
Synchronous Load  
Direct Overriding Clear  
Parallel-to-Serial Conversion  
SER  
V
CC  
SH/LD  
H
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
A
B
C
Q
H
G
D
CLK INH  
CLK  
F
description  
E
GND  
CLR  
The ’HC166 parallel-in or serial-in, serial-out  
registers feature gated clock (CLK, CLK INH)  
inputs and an overriding clear (CLR) input. The  
parallel-in or serial-in modes are established by  
the shift/load (SH/LD) input. When high, SH/LD  
enables the serial (SER) data input and couples  
the eight flip-flops for serial shifting with each  
clock (CLK) pulse. When low, the parallel  
(broadside) data inputs are enabled, and  
synchronous loading occurs on the next clock  
pulse. During parallel loading, serial data flow is  
inhibited. Clocking is accomplished on the  
low-to-high-level edge of CLK through a 2-input  
positive-NORgate permitting one input to be used  
asaclock-enableorclock-inhibitfunction. Holding  
either CLK or CLK INH high inhibits clocking;  
holding either low enables the other clock input.  
This allows the system clock to be free running,  
and the register can be stopped on command with  
the other clock input. CLK INH should be changed  
to the high level only when CLK is high. CLR  
overrides all other inputs, including CLK, and  
resets all flip-flops to zero.  
SN54HC166 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
H
Q
B
4
5
6
7
8
C
NC  
17  
16  
15  
14  
H
NC  
G
D
F
CLK INH  
9 10 11 12 13  
NC – No internal connection  
The SN54HC166 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HC166 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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