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SN54HC03FK PDF预览

SN54HC03FK

更新时间: 2024-10-30 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路输出元件输入元件
页数 文件大小 规格书
4页 69K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES WITH OPEN-DRAIN OUTPUTS

SN54HC03FK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.43
系列:HC/UHJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.0052 A
功能数量:4输入次数:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-DRAIN
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:36 ns
传播延迟(tpd):155 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.03 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.89 mm
Base Number Matches:1

SN54HC03FK 数据手册

 浏览型号SN54HC03FK的Datasheet PDF文件第2页浏览型号SN54HC03FK的Datasheet PDF文件第3页浏览型号SN54HC03FK的Datasheet PDF文件第4页 
SN54HC03, SN74HC03  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
WITH OPEN-DRAIN OUTPUTS  
SCLS077B – MARCH 1984 – REVISED MAY 1997  
SN54HC03 . . . J OR W PACKAGE  
SN74HC03 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
description  
2A  
These devices contain four independent 2-input  
NAND gates. They perform the Boolean function  
Y = A B or Y = A + B in positive logic. The  
open-drain outputs require pullup resistors to  
perform correctly. They may be connected to  
other open-drain outputs to implement active-low  
wired-OR or active-high wired-AND functions.  
2B  
10 3B  
9
8
2Y  
3A  
3Y  
GND  
SN54HC03 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HC03 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC03 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each gate)  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
3B  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
NC – No internal connection  
X
logic symbol  
1
1A  
2
&
3
1Y  
1B  
4
2A  
5
6
2Y  
2B  
9
3A  
8
10  
3Y  
3B  
4A  
4B  
12  
13  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, and W packages.  
logic diagram (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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