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SN54F27FK PDF预览

SN54F27FK

更新时间: 2024-11-05 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
5页 70K
描述
TRIPLE 3-INPUT POSITIVE-NOR GATES

SN54F27FK 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:CERAMIC, QCC-20
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.47
Is Samacsys:N系列:F/FAST
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:NOR GATE
最大I(ol):0.02 A功能数量:3
输入次数:3端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):12 mA
Prop。Delay @ Nom-Sup:6 ns传播延迟(tpd):5.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.03 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

SN54F27FK 数据手册

 浏览型号SN54F27FK的Datasheet PDF文件第2页浏览型号SN54F27FK的Datasheet PDF文件第3页浏览型号SN54F27FK的Datasheet PDF文件第4页浏览型号SN54F27FK的Datasheet PDF文件第5页 
SN54F27, SN74F27  
TRIPLE 3-INPUT POSITIVE-NOR GATES  
SDFS042A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F27 . . . J PACKAGE  
SN74F27 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3C  
3B  
3A  
3Y  
description  
These devices contain three independent 3-input  
NOR gates. They perform the Boolean functions  
Y = A B C or Y = A + B + C in positive logic.  
2Y  
GND  
8
The SN54F27 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F27 is characterized for  
operation from 0°C to 70°C.  
SN54F27 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
INPUTS  
OUTPUT  
Y
2A  
NC  
2B  
1Y  
NC  
3C  
NC  
3B  
4
5
6
7
8
A
H
X
X
L
B
X
H
X
L
C
X
X
H
L
17  
16  
15  
14  
L
L
NC  
2C  
L
9 10 11 12 13  
H
logic symbol  
NC – No internal connection  
1
1A  
1  
2
12  
6
logic diagram, each gate (positive logic)  
1B  
1Y  
2Y  
3Y  
13  
1C  
A
B
C
3
Y
2A  
4
2B  
5
2C  
9
3A  
10  
8
3B  
11  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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