SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071A – AUGUST 1990 – REVISED NOVEMBER 1993
SN54BCT573 . . . J OR W PACKAGE
SN74BCT573 . . . DW OR N PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
1Q
2Q
3Q
4Q
5Q
6Q
• Full Parallel Access for Loading
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and Flatpacks (W), and
Plastic and Ceramic 300-mil DIPs (J, N)
13 7Q
8Q
11 LE
12
description
GND 10
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54BCT573 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
4
5
6
7
8
The eight latches of the ′BCT573 are transparent
D-type latches. While the latch-enable (LE) input
ishigh, theQoutputswillfollowthedata(D)inputs.
When the latch enable is taken low, the Q outputs
will be latched at the logic levels that were set up
at the D inputs.
3D
4D
5D
6D
7D
2Q
3Q
4Q
5Q
6Q
17
16
15
14
9 10 11 12 13
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or
a
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased
drive provide the capability to drive bus lines without need for interface or pullup components.
The output enable (OE) does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN54BCT573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74BCT573 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265