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SN54AS821AFK PDF预览

SN54AS821AFK

更新时间: 2024-11-14 22:59:15
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
6页 95K
描述
10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54AS821AFK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC28,.45SQ
针数:28Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.84系列:AS
JESD-30 代码:S-CQCC-N28长度:11.43 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:55500000 Hz最大I(ol):0.032 A
位数:10功能数量:1
端口数量:2端子数量:28
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC28,.45SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):109 mA
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:2.03 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:11.43 mm
Base Number Matches:1

SN54AS821AFK 数据手册

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SN54AS821A, SN74AS821A  
10-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS230A – DECEMBER 1983 – REVISED AUGUST 1995  
SN54AS821A . . . JT PACKAGE  
SN74AS821A . . . DW OR NT PACKAGE  
(TOP VIEW)  
Functionally Equivalent to AMD’s AM29821  
Provide Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
Outputs Have Undershoot-Protection  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 CLK  
Circuitry  
Power-Up High-Impedance State  
Buffered Control Inputs to Reduce  
dc Loading Effects  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
9D 10  
10D 11  
GND 12  
description  
These 10-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
SN54AS821A . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
5
The ten flip-flops are edge-triggered D-type  
flip-flops. On the positive transition of the clock  
(CLK) input, the Q outputs are true to the data (D)  
input.  
24  
23  
22  
21  
20  
19  
6
7
8
9
10  
11  
A buffered output-enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low logic levels) or a high-  
impedance state. In the high-impedance state, the  
outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without interface or pullup components.  
12 13 14 15 16 17 18  
NC – No internal connection  
OE does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data  
can be entered while the outputs are in the high-impedance state.  
The SN54AS821A is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74AS821A is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
X
X
X
Q
0
H
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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