SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
Bus Transceivers/Registers
Independent Registers and Enables for A
(TOP VIEW)
and B Buses
CLKAB
SAB
OEAB
A1
V
CC
Multiplexed Real-Time and Stored Data
Choice of True or Inverting Data Paths
1
24
23
22
21
20
19
18
17
16
15
14
CLKBA
SBA
OEBA
B1
2
3
Choice of 3-State or Open-Collector
Outputs to A Bus
4
A2
5
Package Options Include Plastic
A3
B2
6
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
A4
B3
7
A5
B4
8
A6
B5
9
A7
B6
10
11
DEVICE
A OUTPUT
B OUTPUT
LOGIC
A8
B7
SN74ALS651A,
’AS651
GND 12
13 B8
3 State
3 State
Inverting
SN54ALS652,
SN74ALS652A,
’AS652
SN54ALS’, SN54AS’ . . . FK PACKAGE
3 State
3 State
True
(TOP VIEW)
’ALS653
Open Collector
Open Collector
3 State
3 State
Inverting
True
SN74ALS654
description
4
3
2 1 28 27 26
5
6
7
8
9
25 OEBA
A1
A2
A3
NC
A4
A5
A6
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low input level selects real-time data, and
a high input level selects stored data. Figure 1
24
23
22
21
20
19
B1
B2
NC
B3
B4
B5
10
11
12 13 14 15 16 17 18
NC – No internal connection
illustrates the four fundamental bus-management functions that can be performed with the octal bus
transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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