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SN54ALS996

更新时间: 2024-09-29 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 锁存器
页数 文件大小 规格书
9页 135K
描述
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

SN54ALS996 数据手册

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SN54ALS996, SN74ALS996  
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES  
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995  
SN54ALS996 . . . JT PACKAGE  
SN74ALS996 . . . DW OR NT PACKAGE  
(TOP VIEW)  
3-State I/O-Type Read-Back Inputs  
Bus-Structured Pinout  
T/C Determines True or Complementary  
Data at Q Outputs  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
EN  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 OE  
14 T/C  
13 CLR  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
description  
These 8-bit latches are designed specifically for  
storing the contents of the input data bus and  
providing the capability of reading back the stored  
data onto the input data bus. The Q outputs are  
designed with bus-driving capability.  
RD 10  
CLK 11  
GND 12  
The edge-triggered flip-flops enter the data on the  
low-to-high transition of the clock (CLK) input  
when the enable (EN) input is low. Data can be  
read back onto the data inputs by taking the read  
(RD) input low, in addition to having EN low. When  
EN is high, both the read-back and write modes  
are disabled. Transitions on EN should only be  
made with CLK high to prevent false clocking.  
SN54ALS996 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
4D  
5D  
6D  
NC  
7D  
8D  
EN  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
5
24  
23  
22  
21  
20  
19  
6
7
The polarity of the Q outputs can be controlled by  
the polarity (T/C) input. When T/C is high, Q is the  
same as is stored in the flip-flops. When T/Cis low,  
the output data is inverted. The Q outputs can be  
placed in the high-impedance state by taking the  
output-enable (OE) input high. OE does not affect  
the internal operation of the register. Old data can  
be retained or new data can be entered while the  
outputs are off.  
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
A low level at the clear (CLR) input resets the  
internal registers low. The clear function is  
asynchronous and overrides all other register  
functions.  
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum  
for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.  
I
OL  
The SN54ALS996 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74ALS996 is characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN54ALS996 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS996 TI

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