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SN54ALS244B PDF预览

SN54ALS244B

更新时间: 2024-11-24 23:06:11
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德州仪器 - TI 驱动器输出元件
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描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54ALS244B 数据手册

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SN54ALS244B, SN54AS244, SN74ALS244B, SN74AS244  
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS  
SDAS142 – D2661, DECEMBER 1982 – REVISED JULY 1987  
SN54ALS244B, SN54AS244 . . . J PACKAGE  
SN74ALS244B, SN74AS244 . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
PNP inputs Reduce DC Loading  
1G  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2G  
Package Options include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1Y1  
A24  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
Dependable Texas instruments Quality and  
Reliability  
description  
These octal buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and transmit-  
ters. Taken together with the ’ALS240A,  
’ALS241A, ’AS240, and ’AS241, these devices  
provide the choice of selected combinations of  
inverting outputs, symmetrical G (active-low input  
control) inputs, and complementary G and G  
inputs.  
SN54ALS244B, SN54AS244 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
The –1 version of the SN74ALS244B is identical  
to the standard version except that the  
9 10 11 12 13  
recommended maximum I  
is increased to  
OL  
48 mA. There is no –1 version of the  
SN54ALS244B.  
The SN54ALS244B and SN54AS244 are characterized for operation over the full military temperature range  
of 55°C to 125°C. The SN74ALS244B and SN74AS244 are characterized for operation from 0°C to 70°C.  
logic symbol  
1
1
2
1G  
EN  
1G  
2
4
6
8
18  
16  
14  
12  
18  
16  
14  
12  
1A1  
1Y1  
1Y2  
1Y3  
1Y4  
1A1  
1A2  
1A3  
1A4  
1Y1  
1Y2  
1Y3  
1Y4  
4
6
8
1A2  
1A3  
1A4  
19  
2G  
EN  
19  
11  
11  
13  
15  
17  
9
7
5
3
2G  
2A1  
2A2  
2A3  
2A4  
2Y1  
2Y2  
2Y3  
2Y4  
9
7
5
3
1Y1  
1Y2  
1Y3  
1Y4  
2A1  
13  
15  
17  
2A2  
2A3  
2A4  
† This is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers are for DW, J, and N packages.  
Copyright 1987, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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