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SN54ALS113AFK PDF预览

SN54ALS113AFK

更新时间: 2024-11-04 19:54:11
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
4页 55K
描述
ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC, LCC-20

SN54ALS113AFK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.91
系列:ALSJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:J-K FLIP-FLOP位数:2
功能数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):4.5 mA传播延迟(tpd):23 ns
认证状态:Not Qualified座面最大高度:2.03 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:8.89 mm最小 fmax:25 MHz
Base Number Matches:1

SN54ALS113AFK 数据手册

 浏览型号SN54ALS113AFK的Datasheet PDF文件第2页浏览型号SN54ALS113AFK的Datasheet PDF文件第3页浏览型号SN54ALS113AFK的Datasheet PDF文件第4页 
SN54ALS113A, SN74ALS113A  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH PRESET  
SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986  
Fully Buffered to Offer Maximum isolation  
SN54ALS113A . . . J PACKAGE  
SN74ALS113A . . . D OR N PACKAGE  
from External Disturbance  
(TOP VIEW)  
Package Options Include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1 CLK  
1K  
1J  
1PRE  
1Q  
CC  
2CLK  
2K  
2J  
2PRE  
2Q  
Dependable Texas Instruments Quality and  
Reliability  
1Q  
GND  
TYPICAL POWER  
DISSIPATION  
PER FLIP-FLOP  
TYPICAL MAXIMUM  
CLOCK FREQUENCY  
TYPE  
2Q  
8
’ALS113A  
40 MHz (C =15 pF)  
6 mW  
L
SN54ALS113A . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the Preset input sets the outputs regardless of the  
levels of the other inputs. When Preset PRE is  
inactive (high), data at the J and K inputs meeting  
the setup time requirements are transferred to the  
outputs on the negative-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the fall time of the  
clock pulse. Following the hold time interval, data  
at the J and K inputs may be changed without  
affecting the levels at the outputs. These versatile  
flip-flops can perform as toggle flip-flops by tying  
J and K high.  
3
2
1
20 19  
18  
2K  
1J  
NC  
4
5
6
7
8
NC  
2J  
17  
16  
15  
14  
1PRE  
NC  
NC  
2PRE  
1Q  
9 10 11 12 13  
NC–No internal connection  
logic symbol  
The SN54ALS113A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS113A is characterized for  
operation from 0°C to 70°C.  
4
3
S
1PRE  
1J  
5
1Q  
1J  
1
2
C1  
1K  
1CLK  
1K  
FUNCTION TABLE  
6
9
8
1Q  
2Q  
2Q  
INPUTS  
OUTPUTS  
10  
PRE  
L
CLK  
J
X
L
K
X
L
Q
Q
2PRE  
2J  
X
H
L
11  
13  
H
Q
Q
0
0
2CLK  
2K  
H
H
L
L
H
L
12  
H
H
H
X
L
H
H
H
X
TOGGLE  
H
H
Q
Q
0
0
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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