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SN54ALS10AFK PDF预览

SN54ALS10AFK

更新时间: 2024-09-15 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 栅极输入元件
页数 文件大小 规格书
6页 98K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54ALS10AFK 技术参数

生命周期:Obsolete零件包装代码:QFN
包装说明:QCCN, LCC20,.35SQ针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.31Is Samacsys:N
系列:ALSJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:3
输入次数:3端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
最大电源电流(ICC):2.2 mAProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.03 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mmBase Number Matches:1

SN54ALS10AFK 数据手册

 浏览型号SN54ALS10AFK的Datasheet PDF文件第2页浏览型号SN54ALS10AFK的Datasheet PDF文件第3页浏览型号SN54ALS10AFK的Datasheet PDF文件第4页浏览型号SN54ALS10AFK的Datasheet PDF文件第5页浏览型号SN54ALS10AFK的Datasheet PDF文件第6页 
SN54ALS10A, SN54AS10, SN74ALS10A, SN74AS10  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SDAS002B – MARCH 1984 – REVISED DECEMBER 1994  
SN54ALS10A, SN54AS10 . . . J PACKAGE  
SN74ALS10A, SN74AS10 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3C  
3B  
3A  
3Y  
description  
2A  
2B  
These devices contain three independent 3-input  
positive-NAND gates. They perform the Boolean  
functions Y = A B C or Y = A + B + C in positive  
logic.  
2C  
2Y  
GND  
8
The SN54ALS10A and SN54AS10 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS10A and SN74AS10 are characterized  
for operation from 0°C to 70°C.  
SN54ALS10A, SN54AS10 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
FUNCTION TABLE  
(each gate)  
2A  
NC  
2B  
4
5
6
7
8
1Y  
NC  
3C  
NC  
3B  
17  
16  
15  
14  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
NC  
2C  
L
H
H
H
9 10 11 12 13  
X
X
X
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
1A  
&
2
2
12  
12  
6
1B  
1C  
1Y  
2Y  
3Y  
1B  
1Y  
2Y  
3Y  
13  
13  
1C  
3
3
4
5
2A  
4
2A  
6
2B  
5
2B  
2C  
2C  
9
3A  
9
10  
8
3A  
3B  
3C  
3B  
10  
11  
8
11  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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